Renshen Wang

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6EERenshen Wang, Chung-Kuan Cheng: Octilinear redistributive routing in bump arrays. ACM Great Lakes Symposium on VLSI 2009: 191-196
5EERenshen Wang, Chung-Kuan Cheng: On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design. ACM Great Lakes Symposium on VLSI 2009: 257-262
4EELing Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng: Low Power Passive Equalizer Design for Computer Memory Links. Hot Interconnects 2008: 51-56
3EERenshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng: 3-D floorplanning using labeled tree and dual sequences. ISPD 2008: 54-59
2EERenshen Wang, Rui Shi, Chung-Kuan Cheng: Layer minimization of escape routing in area array packaging. ICCAD 2006: 815-819
1EERenshen Wang, Sheqin Dong, Xianlong Hong: An improved P-admissible floorplan representation based on Corner Block List. ASP-DAC 2005: 1115-1118

Coauthor Index

1James F. Buckwalter [4]
2Chung-Kuan Cheng [2] [3] [4] [5] [6]
3Fan R. K. Chung (Fan Chung Graham) [3]
4Alina Deutsch [4]
5Sheqin Dong [1]
6Daniel M. Dreps [4]
7Ronald L. Graham [3]
8Xianlong Hong [1]
9George A. Katopis [4]
10Ernest S. Kuh [4]
11Rui Shi [2]
12Evangeline F. Y. Young (F. Y. Young, Fung Yu Young) [3]
13Wenjian Yu [4]
14Ling Zhang [4]
15Yulei Zhang [4]
16Yi Zhu [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)