| 2005 |
|---|
| 9 | EE | Peter Bellows:
High-Visibility Debug-By-Design for FPGA Platforms.
The Journal of Supercomputing 32(2): 105-118 (2005) |
| 2004 |
|---|
| 8 | | Peter Bellows:
Distinguished Paper: High-Visibility Debug-by-Design for FPGA Platforms.
ERSA 2004: 247-258 |
| 2003 |
|---|
| 7 | EE | Peter Bellows,
Jaroslav Flidr,
Ladan Gharai,
Colin Perkins,
Pawel Chodowiec,
Kris Gaj:
IPsec-Protected Transport of HDTV over IP.
FPL 2003: 869-879 |
| 2002 |
|---|
| 6 | EE | Peter Bellows,
Jaroslav Flidr,
Tom Lehman,
Brian Schott,
Keith D. Underwood:
GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing.
FCCM 2002: 121-130 |
| 5 | EE | Tim Grembowski,
Roar Lien,
Kris Gaj,
Nghi Nguyen,
Peter Bellows,
Jaroslav Flidr,
Tom Lehman,
Brian Schott:
Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512.
ISC 2002: 75-89 |
| 2001 |
|---|
| 4 | EE | Pawel Chodowiec,
Kris Gaj,
Peter Bellows,
Brian Schott:
Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board.
ISC 2001: 220-234 |
| 3 | EE | Peter Bellows,
Brad L. Hutchings:
Designing Run-Time Reconfigurable Systems with JHDL.
VLSI Signal Processing 28(1-2): 29-45 (2001) |
| 1999 |
|---|
| 2 | EE | Brad L. Hutchings,
Peter Bellows,
Joseph Hawkins,
K. Scott Hemmert,
Brent E. Nelson,
Mike Rytting:
A CAD Suite for High-Performance FPGA Design.
FCCM 1999: 12-24 |
| 1998 |
|---|
| 1 | EE | Peter Bellows,
Brad L. Hutchings:
JHDL - An HDL for Reconfigurable Systems.
FCCM 1998: 175- |
