| 2007 |
|---|
| 6 | EE | M. Marshall,
G. Russell:
A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor.
DSD 2007: 649-656 |
| 2004 |
|---|
| 5 | EE | P. D. Hyde,
G. Russell:
ASSEC: An Asynchronous Self-Checking RISC-based Processor.
DSD 2004: 104-111 |
| 4 | EE | P. D. Hyde,
G. Russell:
A Comparative Study of the Design of Synchronous and Asynchronous Self-Checking RISC Processors.
IOLTS 2004: 89-94 |
| 1999 |
|---|
| 3 | EE | A. Maamar,
G. Russell:
ADOLT - An ADaptable On - Line Testing Scheme for VLSI Circuits.
DATE 1999: 770-771 |
| 1998 |
|---|
| 2 | EE | A. Maamar,
G. Russell:
A 32-Bit Risc Processor with Concurrent Error Detection.
EUROMICRO 1998: 10461-10467 |
| 1992 |
|---|
| 1 | EE | G. Russell:
CAD accelerators: A P Ambler, P Agrawal and W R Moore (Eds.) Elsevier, Netherlands (1991), 300 pp, ISBN 0444889647.
Computer-Aided Design 24(8): 454 (1992) |
