| 2004 |
|---|
| 12 | EE | Jayapreetha Natesan,
Damu Radhakrishnan:
Shift Invert Coding (SINV) for Low Power VLSI.
DSD 2004: 190-194 |
| 11 | | S. Castillo,
Naveen K. Samala,
K. Manwaring,
Baback A. Izadi,
Damu Radhakrishnan:
Experimental Analysis of Batteries Under Continuous and Intermittent Operations.
ESA/VLSI 2004: 18-24 |
| 10 | | Naveen K. Samala,
Damu Radhakrishnan,
Baback A. Izadi:
A Low Energy Deep Sub-Micron Bus Coding Technique.
ESA/VLSI 2004: 25-30 |
| 9 | | Yong Liu,
Edmund Ming-Kit Lai,
A. Benjamin Premkumar,
Damu Radhakrishnan:
A Low-Power Pipelined Implementation of 2D Discrete Wavelet Transform.
ESA/VLSI 2004: 40-46 |
| 8 | | R. V. Menon,
S. Chennupati,
Naveen K. Samala,
Damu Radhakrishnan,
Baback A. Izadi:
Switching Activity Minimization in Combinational Logic Design.
ESA/VLSI 2004: 47-53 |
| 7 | | Jayapreetha Natesan,
Damu Radhakrishnan:
A Novel Bus Encoding Technique for Low Power VLSI.
ESA/VLSI 2004: 54-62 |
| 2003 |
|---|
| 6 | | R. V. Menon,
S. Chennupati,
Naveen K. Samala,
Damu Radhakrishnan,
Baback A. Izadi:
Power Optimized Combinational Logic Design.
Embedded Systems and Applications 2003: 223-227 |
| 5 | | Saumya Uppaluri,
Baback A. Izadi,
Damu Radhakrishnan:
Low-Power Dynamic Scheduling in Heterogeneous Systems.
Embedded Systems and Applications 2003: 261-267 |
| 2001 |
|---|
| 4 | EE | A. P. Preethy,
Damu Radhakrishnan,
Amos Omondi:
A high performance RNS multiply-accumulate unit.
ACM Great Lakes Symposium on VLSI 2001: 145-148 |
| 3 | EE | A. P. Preethy,
Damu Radhakrishnan,
Amos Omondi:
Fault-tolerance scheme for an RNS MAC: performance and cost analysis.
ISCAS (2) 2001: 717-720 |
| 1999 |
|---|
| 2 | EE | Damu Radhakrishnan,
A. P. Preethy:
A Parallel Approach to Direct Analog-to-Residue Conversion.
Inf. Process. Lett. 69(5): 249-252 (1999) |
| 1985 |
|---|
| 1 | | Ali Feizi,
Damu Radhakrishnan:
Multiple Output Pass Networks: Design and Testing.
ITC 1985: 907-911 |
