| |
| 2006 | ||
|---|---|---|
| 3 | EE | Luo Jianwen, Jong Ching Chuen: Matrix Inversion on Reconfigurable Hardware using Binary-coded z-path CORDIC. APCCAS 2006: 1176-1179 |
| 2004 | ||
| 2 | EE | Luo Jianwen, Jong Ching Chuen: Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs. DSD 2004: 244-248 |
| 2002 | ||
| 1 | EE | Zhaoxuan Shen, Jong Ching Chuen: Lower Bound Estimation of Hardware Resources for Scheduling in High-Level Synthesis. J. Comput. Sci. Technol. 17(6): 718-730 (2002) |
| 1 | Luo Jianwen | [2] [3] |
| 2 | Zhaoxuan Shen | [1] |