| |
| 2000 | ||
|---|---|---|
| 2 | EE | Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang: "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED 2000: 203-206 |
| 1 | EE | Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang: A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design 2000: 44-49 |
| 1 | Ching-Te Chuang | [1] [2] |
| 2 | Wei Hwang | [1] [2] |
| 3 | Rajiv V. Joshi | [1] [2] |
| 4 | Ghavam V. Shahidi | [1] |