2009 |
16 | EE | Mike Wu,
Abhishek Ranjan,
Khai N. Truong:
An exploration of social requirements for exercise group formation.
CHI 2009: 79-82 |
2008 |
15 | EE | Abhishek Ranjan,
Jeremy P. Birnholtz,
Ravin Balakrishnan:
Improving meeting capture by applying television production principles with audio and motion detection.
CHI 2008: 227-236 |
2007 |
14 | EE | Abhishek Ranjan,
Jeremy P. Birnholtz,
Ravin Balakrishnan:
Dynamic shared visual spaces: experimenting with automatic camera control in a remote repair task.
CHI 2007: 1177-1186 |
2006 |
13 | EE | Abhishek Ranjan,
Ravin Balakrishnan,
Mark H. Chignell:
Searching in audio: the utility of transcripts, dichotic presentation, and time-compression.
CHI 2006: 721-730 |
12 | EE | Abhishek Ranjan,
Jeremy P. Birnholtz,
Ravin Balakrishnan:
An exploratory analysis of partner action and camera control in a video-mediated collaborative task.
CSCW 2006: 403-412 |
11 | EE | Amlan Ghosh,
Abhishek Ranjan,
Nirmal B. Chakrabarti:
Design and Implementation of Analog Multitone Signal Generator Using Regenerative Frequency Divider for OFDM Transceiver.
DELTA 2006: 23-30 |
2005 |
10 | EE | Shahzad Malik,
Abhishek Ranjan,
Ravin Balakrishnan:
Interacting with large displays from a distance with vision-tracked multi-finger gestural input.
UIST 2005: 43-52 |
2004 |
9 | EE | Steve Tsang,
Ravin Balakrishnan,
Karan Singh,
Abhishek Ranjan:
A suggestive interface for image guided 3D sketching.
CHI 2004: 591-598 |
8 | EE | Navaratnasothie Selvakkumaran,
Abhishek Ranjan,
Salil Raje,
George Karypis:
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources.
DAC 2004: 741-746 |
7 | EE | Navaratnasothie Selvakkumaran,
Abhishek Ranjan,
Salil Raje,
George Karypis:
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources.
FPGA 2004: 253 |
6 | EE | Taraneh Taghavi,
Soheil Ghiasi,
Abhishek Ranjan,
Salil Raje,
Majid Sarrafzadeh:
Innovate or perish: FPGA physical design.
ISPD 2004: 148-155 |
2003 |
5 | EE | Maogang Wang,
Abhishek Ranjan,
Salil Raje:
Multi-Million Gate FPGA Physical Design Challenges.
ICCAD 2003: 891-899 |
2001 |
4 | EE | Abhishek Ranjan,
Ankur Srivastava,
V. Karnam,
Majid Sarrafzadeh:
Layout aware retiming.
ACM Great Lakes Symposium on VLSI 2001: 25-30 |
3 | EE | Abhishek Ranjan,
Kia Bazargan,
S. Ogrenci,
Majid Sarrafzadeh:
Fast floorplanning for effective prediction and construction.
IEEE Trans. VLSI Syst. 9(2): 341-351 (2001) |
2000 |
2 | EE | Kia Bazargan,
Abhishek Ranjan,
Majid Sarrafzadeh:
Fast and accurate estimation of floorplans in logic/high-level synthesis.
ACM Great Lakes Symposium on VLSI 2000: 95-100 |
1 | EE | Abhishek Ranjan,
Kia Bazargan,
Majid Sarrafzadeh:
Fast Hierarchical Floorplanning with Congestion and Timing Control.
ICCD 2000: 357-362 |