2009 |
24 | EE | Vijay Janapa Reddi,
Meeta Sharma Gupta,
Glenn H. Holloway,
Gu-Yeon Wei,
Michael D. Smith,
David Brooks:
Voltage emergency prediction: Using signatures to reduce operating margins.
HPCA 2009: 18-29 |
23 | EE | Kevin Brownell,
Ali Durlov Khan,
David Brooks,
Gu-Yeon Wei:
Place and route considerations for voltage interpolated designs.
ISQED 2009: 594-600 |
2008 |
22 | EE | Wonyoung Kim,
Meeta Sharma Gupta,
Gu-Yeon Wei,
David Brooks:
System level analysis of fast, per-core DVFS using on-chip switching regulators.
HPCA 2008: 123-134 |
21 | EE | Meeta Sharma Gupta,
Krishna K. Rangan,
Michael D. Smith,
Gu-Yeon Wei,
David M. Brooks:
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors.
HPCA 2008: 381-392 |
20 | EE | Kevin Brownell,
Gu-Yeon Wei,
David Brooks:
Evaluation of voltage interpolation to address process variations.
ICCAD 2008: 529-536 |
19 | EE | Michael Karpelson,
Gu-Yeon Wei,
Robert J. Wood:
A review of actuation and power electronics options for flapping-wing robotic insects.
ICRA 2008: 779-786 |
18 | EE | Xiaoyao Liang,
Gu-Yeon Wei,
David Brooks:
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency.
ISCA 2008: 191-202 |
17 | EE | Mark Hempstead,
Gu-Yeon Wei,
David Brooks:
System design considerations for sensor network applications.
ISCAS 2008: 2566-2569 |
16 | EE | Xuning Chen,
Gu-Yeon Wei,
Li-Shiuan Peh:
Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies.
ISLPED 2008: 277-282 |
15 | EE | Gu-Yeon Wei,
David Brooks,
Ali Durlov Khan,
Xiaoyao Liang:
Instruction-driven clock scheduling with glitch mitigation.
ISLPED 2008: 357-362 |
14 | EE | Xiaoyao Liang,
Ramon Canal,
Gu-Yeon Wei,
David Brooks:
Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
IEEE Micro 28(1): 60-68 (2008) |
2007 |
13 | EE | Meeta Sharma Gupta,
Jarod L. Oatley,
Russ Joseph,
Gu-Yeon Wei,
David M. Brooks:
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network.
DATE 2007: 624-629 |
12 | EE | Ruwan N. S. Ratnayake,
Erich F. Haratsch,
Gu-Yeon Wei:
A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders.
GLOBECOM 2007: 265-270 |
11 | EE | Ruwan N. S. Ratnayake,
Erich F. Haratsch,
Gu-Yeon Wei:
Serial Sum-Product Architecture for Low-Density Parity-Check Codes.
ICCCN 2007: 154-158 |
10 | EE | Meeta Sharma Gupta,
Krishna K. Rangan,
Michael D. Smith,
Gu-Yeon Wei,
David Brooks:
Towards a software approach to mitigate voltage emergencies.
ISLPED 2007: 123-128 |
9 | EE | Xiaoyao Liang,
Ramon Canal,
Gu-Yeon Wei,
David Brooks:
Process Variation Tolerant 3T1D-Based Cache Architectures.
MICRO 2007: 15-26 |
2006 |
8 | EE | Mark Hempstead,
Gu-Yeon Wei,
David Brooks:
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations.
CASES 2006: 368-378 |
7 | EE | Wai-Chi Fang,
Sharon Kedar,
Susan Owen,
Gu-Yeon Wei,
David Brooks,
Jonathan Lees:
System-on-Chip Architecture Design for Intelligent Sensor Networks.
IIH-MSP 2006: 579-582 |
2005 |
6 | EE | Xuning Chen,
Li-Shiuan Peh,
Gu-Yeon Wei,
Yue-Kai Huang,
Paul R. Prucnal:
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems.
HPCA 2005: 120-131 |
5 | EE | Mark Hempstead,
Nikhil Tripathi,
Patrick Mauro,
Gu-Yeon Wei,
David Brooks:
An Ultra Low Power System Architecture for Sensor Network Applications.
ISCA 2005: 208-219 |
2004 |
4 | | Ruwan N. S. Ratnayake,
Gu-Yeon Wei,
Aleksandar Kavcic:
Pipelined parallel architecture for high throughput MAP detectors.
ISCAS (2) 2004: 505-508 |
3 | | Pavan Kumar Hanumolu,
Bryan Casper,
Randy Mooney,
Gu-Yeon Wei,
Un-Ku Moon:
Jitter in high-speed serial and parallel links.
ISCAS (4) 2004: 425-428 |
2 | | Yong-Cheol Bae,
Gu-Yeon Wei:
A mixed PLL/DLL architecture for low jitter clock generation.
ISCAS (4) 2004: 788-791 |
1996 |
1 | EE | Gu-Yeon Wei,
Mark Horowitz:
A low power switching power supply for self-clocked systems.
ISLPED 1996: 313-317 |