| 2009 |
| 43 | EE | Sangmin Seo,
Jaejin Lee,
Zehra Sura:
Design and implementation of software-managed caches for multicores with local memory.
HPCA 2009: 55-66 |
| 2008 |
| 42 | EE | Bernhard Egger,
Jaejin Lee,
Heonshik Shin:
Scratchpad memory management in a multitasking environment.
EMSOFT 2008: 265-274 |
| 41 | EE | Jaejin Lee,
Junghyun Kim,
Choonki Jang,
Seungkyun Kim,
Bernhard Egger,
Kwangsub Kim,
Sangyong Han:
FaCSim: a fast and cycle-accurate architecture simulator for embedded systems.
LCTES 2008: 89-100 |
| 40 | EE | Jaejin Lee,
Sangmin Seo,
Chihun Kim,
Junghyun Kim,
Posung Chun,
Zehra Sura,
Jungwon Kim,
Sangyong Han:
COMIC: a coherent shared memory interface for cell be.
PACT 2008: 303-314 |
| 39 | EE | Bernhard Egger,
Jaejin Lee,
Heonshik Shin:
Dynamic scratchpad memory management for code in portable systems with an MMU.
ACM Trans. Embedded Comput. Syst. 7(2): (2008) |
| 2007 |
| 38 | EE | Hyungmin Cho,
Bernhard Egger,
Jaejin Lee,
Heonshik Shin:
Dynamic data scratchpad memory management for a memory subsystem with an MMU.
LCTES 2007: 195-206 |
| 37 | EE | Sheayun Lee,
Jaejin Lee,
Chang Yun Park,
Sang Lyul Min:
Selective code transformation for dual instruction set processors.
ACM Trans. Embedded Comput. Syst. 6(2): (2007) |
| 2006 |
| 36 | EE | Bernhard Egger,
Chihun Kim,
Choonki Jang,
Yoonsung Nam,
Jaejin Lee,
Sang Lyul Min:
A dynamic code placement technique for scratchpad memory using postpass optimization.
CASES 2006: 223-233 |
| 35 | EE | Bernhard Egger,
Jaejin Lee,
Heonshik Shin:
Scratchpad memory management for portable systems with a memory management unit.
EMSOFT 2006: 321-330 |
| 34 | EE | Changhee Jung,
Daeseob Lim,
Jaejin Lee,
Yan Solihin:
Helper thread prefetching for loosely-coupled multiprocessor systems.
IPDPS 2006 |
| 33 | EE | Bruce E. Sagan,
Jaejin Lee:
An algorithmic sign-reversing involution for special rim-hook tableaux.
J. Algorithms 59(2): 149-161 (2006) |
| 2005 |
| 32 | EE | Chi-Leung Wong,
Zehra Sura,
Xing Fang,
Kyungwoo Lee,
Samuel P. Midkiff,
Jaejin Lee,
David A. Padua:
Evaluating the Impact of Thread Escape Analysis on a Memory Consistency Model-Aware Compiler.
LCPC 2005: 170-184 |
| 31 | EE | Zehra Sura,
Xing Fang,
Chi-Leung Wong,
Samuel P. Midkiff,
Jaejin Lee,
David A. Padua:
Compiler techniques for high performance sequentially consistent java programs.
PPOPP 2005: 2-13 |
| 30 | EE | Changhee Jung,
Daeseob Lim,
Jaejin Lee,
Sangyong Han:
Adaptive execution techniques for SMT multiprocessor architectures.
PPOPP 2005: 236-246 |
| 29 | EE | Mazen Kharbutli,
Yan Solihin,
Jaejin Lee:
Eliminating Conflict Misses Using Prime Number-Based Cache Indexing.
IEEE Trans. Computers 54(5): 573-586 (2005) |
| 2004 |
| 28 | EE | Chanik Park,
Junghee Lim,
Kiwon Kwon,
Jaejin Lee,
Sang Lyul Min:
Compiler-assisted demand paging for embedded systems with flash memory.
EMSOFT 2004: 114-124 |
| 27 | EE | Mazen Kharbutli,
Keith Irwin,
Yan Solihin,
Jaejin Lee:
Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses.
HPCA 2004: 288-299 |
| 26 | EE | Sheayun Lee,
Jaejin Lee,
Chang Yun Park,
Sang Lyul Min:
A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor.
SCOPES 2004: 244-258 |
| 25 | EE | Samuel P. Midkiff,
Jaejin Lee,
David A. Padua:
A compiler for multiple memory models.
Concurrency and Computation: Practice and Experience 16(2-3): 197-220 (2004) |
| 2003 |
| 24 | EE | Hyun Yoe,
Jaejin Lee:
Design of VDSL Networks for the High Speed Internet Services.
GCC (2) 2003: 442-445 |
| 23 | EE | Xing Fang,
Jaejin Lee,
Samuel P. Midkiff:
Automatic fence insertion for shared memory multiprocessing.
ICS 2003: 285-294 |
| 22 | EE | Sheayun Lee,
Jaejin Lee,
Sang Lyul Min,
Jason Hiser,
Jack W. Davidson:
Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation.
SCOPES 2003: 33-48 |
| 21 | | Sheayun Lee,
Jaejin Lee,
Chang Yun Park,
Sang Lyul Min:
A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors.
WCET 2003: 91-94 |
| 20 | EE | Yan Solihin,
Jaejin Lee,
Josep Torrellas:
Correlation Prefetching with a User-Level Memory Thread.
IEEE Trans. Parallel Distrib. Syst. 14(6): 563-580 (2003) |
| 2002 |
| 19 | EE | Yan Solihin,
Josep Torrellas,
Jaejin Lee:
Using a User-Level Memory Thread for Correlation Prefetching.
ISCA 2002: 171-182 |
| 18 | EE | Chi-Leung Wong,
Zehra Sura,
David A. Padua,
Xing Fang,
Jaejin Lee,
Samuel P. Midkiff:
The Pensieve Project: A Compiler Infrastructure for Memory Models.
ISPAN 2002: 239-244 |
| 17 | EE | Zehra Sura,
Chi-Leung Wong,
Xing Fang,
Jaejin Lee,
Samuel P. Midkiff,
David A. Padua:
Automatic Implementation of Programming Language Consistency Models.
LCPC 2002: 172-187 |
| 16 | EE | Jaejin Lee,
H. D. K. Moonesinghe:
Adaptively Increasing Performance and Scalability of Automatically Parallelized Programs.
LCPC 2002: 203-217 |
| 15 | EE | Ji Zhang,
Jaejin Lee,
Philip K. McKinley:
Optimizing the Java Piped I/O Stream Library for Performance.
LCPC 2002: 233-248 |
| 2001 |
| 14 | EE | Jaejin Lee,
Yan Solihin,
Josep Torrellas:
Automatically Mapping Code on an Intelligent Memory Architecture.
HPCA 2001: 121- |
| 13 | EE | Jun Lee,
Hyuntae Kim,
Jaejin Lee:
Information extraction method without original image using turbo code.
ICIP (3) 2001: 880-883 |
| 12 | EE | Dug Hun Hong,
Jaejin Lee:
A convergence of geometric mean for T-related fuzzy numbers.
Fuzzy Sets and Systems 121(3): 537-543 (2001) |
| 11 | EE | Yan Solihin,
Jaejin Lee,
Josep Torrellas:
Automatic Code Mapping on an Intelligent Memory Architecture.
IEEE Trans. Computers 50(11): 1248-1266 (2001) |
| 10 | EE | Jaejin Lee,
David A. Padua:
Hiding Relaxed Memory Consistency with a Compiler.
IEEE Trans. Computers 50(8): 824-833 (2001) |
| 2000 |
| 9 | | Jaejin Lee,
Chee Sun Won:
Image Integrity and Correction using Parities of Error Control Coding.
IEEE International Conference on Multimedia and Expo (III) 2000: 1297-1300 |
| 8 | EE | Jaejin Lee,
David A. Padua:
Hiding Relaxed Memory Consistency with Compilers.
IEEE PACT 2000: 111-122 |
| 7 | EE | Yan Solihin,
Jaejin Lee,
Josep Torrellas:
Adaptively Mapping Code in an Intelligent Memory Architecture.
Intelligent Memory Systems 2000: 71-84 |
| 1999 |
| 6 | EE | Jaejin Lee,
David A. Padua,
Samuel P. Midkiff:
Basic Compiler Algorithms for Parallel Programs.
PPOPP 1999: 1-12 |
| 1998 |
| 5 | | Jaejin Lee,
Samuel P. Midkiff,
David A. Padua:
A Constant Propagation Algorithm for Explicitly Parallel Programs.
International Journal of Parallel Programming 26(5): 563-589 (1998) |
| 1997 |
| 4 | | Jaejin Lee,
Samuel P. Midkiff,
David A. Padua:
Concurrent Static Single Assignment Form and Constant Propagation for Explicitly Parallel Programs.
LCPC 1997: 114-130 |
| 1996 |
| 3 | | William Blume,
Rudolf Eigenmann,
Keith Faigin,
John Grout,
Jaejin Lee,
Thomas Lawrence,
Jay Hoeflinger,
David A. Padua,
Yunheung Paek,
Paul Petersen,
William M. Pottenger,
Lawrence Rauchwerger,
Peng Tu,
Stephen Weatherford:
Restructuring Programs for High-Speed Computers with Polaris.
ICPP Workshop 1996: 149-161 |
| 2 | | William Blume,
Ramon Doallo,
Rudolf Eigenmann,
John Grout,
Jay Hoeflinger,
Thomas Lawrence,
Jaejin Lee,
David A. Padua,
Yunheung Paek,
William M. Pottenger,
Lawrence Rauchwerger,
Peng Tu:
Parallel Programming with Polaris.
IEEE Computer 29(12): 87-81 (1996) |
| 1995 |
| 1 | | Zohar Manna,
Nikolaj Bjørner,
Anca Browne,
Edward Y. Chang,
Michael Colón,
Luca de Alfaro,
Harish Devarajan,
Arjun Kapur,
Jaejin Lee,
Henny Sipma,
Tomás E. Uribe:
STeP: The Stanford Temporal Prover.
TAPSOFT 1995: 793-794 |