2009 |
14 | EE | Michael D. Powell,
Arijit Biswas,
Joel S. Emer,
Shubhendu S. Mukherjee,
Basit R. Sheikh,
Shrirang M. Yardi:
CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.
HPCA 2009: 289-300 |
2007 |
13 | EE | Michael D. Powell,
T. N. Vijaykumar:
Resource area dilation to reduce power density in throughput servers.
ISLPED 2007: 268-273 |
2005 |
12 | EE | Zeshan Chishti,
Michael D. Powell,
T. N. Vijaykumar:
Optimizing Replication, Communication, and Capacity Allocation in CMPs.
ISCA 2005: 357-368 |
11 | EE | Michael D. Powell,
Ethan Schuchman,
T. N. Vijaykumar:
Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines.
MICRO 2005: 294-304 |
2004 |
10 | EE | Mohamed A. Gomaa,
Michael D. Powell,
T. N. Vijaykumar:
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system.
ASPLOS 2004: 260-270 |
9 | EE | Michael D. Powell,
T. N. Vijaykumar:
Exploiting Resonant Behavior to Reduce Inductive Noise.
ISCA 2004: 288-301 |
2003 |
8 | EE | Michael D. Powell,
T. N. Vijaykumar:
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage.
ISCA 2003: 72-83 |
7 | EE | Michael D. Powell,
T. N. Vijaykumar:
Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise.
ISLPED 2003: 223-228 |
6 | EE | Zeshan Chishti,
Michael D. Powell,
T. N. Vijaykumar:
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures.
MICRO 2003: 55-66 |
2002 |
5 | EE | Se-Hyun Yang,
Michael D. Powell,
Babak Falsafi,
T. N. Vijaykumar:
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay.
HPCA 2002: 151- |
4 | EE | Il Park,
Michael D. Powell,
T. N. Vijaykumar:
Reducing register ports for higher speed and lower energy.
MICRO 2002: 171-182 |
2001 |
3 | EE | Se-Hyun Yang,
Michael D. Powell,
Babak Falsafi,
Kaushik Roy,
T. N. Vijaykumar:
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches.
HPCA 2001: 147-158 |
2 | EE | Michael D. Powell,
Amit Agarwal,
T. N. Vijaykumar,
Babak Falsafi,
Kaushik Roy:
Reducing set-associative cache energy via way-prediction and selective direct-mapping.
MICRO 2001: 54-65 |
1 | EE | Michael D. Powell,
Se-Hyun Yang,
Babak Falsafi,
Kaushik Roy,
T. N. Vijaykumar:
Reducing leakage in a high-performance deep-submicron instruction cache.
IEEE Trans. VLSI Syst. 9(1): 77-89 (2001) |