2009 |
20 | EE | Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano,
Tsutomu Yoshinaga:
Prediction router: Yet another low latency on-chip router architecture.
HPCA 2009: 367-378 |
2008 |
19 | EE | Ben A. Abderazek,
Arquimedes Canedo,
Tsutomu Yoshinaga,
Masahiro Sowa:
The QC-2 parallel Queue processor architecture.
J. Parallel Distrib. Comput. 68(2): 235-245 (2008) |
2007 |
18 | EE | Ben A. Abderazek,
Mushfiquzzaman Akanda,
Tsutomu Yoshinaga,
Masahiro Sowa:
Mathematical Model for Multiobjective Synthesis of NoC Architectures.
ICPP Workshops 2007: 36 |
2006 |
17 | EE | Ben A. Abderazek,
Tsutomu Yoshinaga,
Masahiro Sowa:
Scalable Core-Based Methodology and Synthesizable Core for Systematic Design.
ICPP Workshops 2006: 345-352 |
16 | EE | Ben A. Abderazek,
Tsutomu Yoshinaga,
Masahiro Sowa:
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.
The Journal of Supercomputing 38(1): 3-15 (2006) |
2005 |
15 | EE | Ben A. Abderazek,
Sotaro Kawata,
Tsutomu Yoshinaga,
Masahiro Sowa:
Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.
EUC 2005: 340-349 |
14 | | Ta Quoc Viet,
Tsutomu Yoshinaga:
Asynchronous Parallel Programming Model for SMP Clusters.
IASTED PDCS 2005: 355-360 |
13 | EE | Masahiro Sowa,
Ben A. Abderazek,
Tsutomu Yoshinaga:
Parallel Queue Processor Architecture Based on Produced Order Computation Model.
The Journal of Supercomputing 32(3): 217-229 (2005) |
2003 |
12 | EE | Ben A. Abderazek,
Soichi Shigeta,
Tsutomu Yoshinaga,
Masahiro Sowa:
On the Design of a Register Queue Based Processor Architecture (FaRM-rq).
ISPA 2003: 248-262 |
2002 |
11 | EE | Takashi Yokota,
Masamichi Nagafuchi,
Yoshito Mekada,
Tsutomu Yoshinaga,
Kanemitsu Ootsu,
Takanobu Baba:
A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing.
FCCM 2002: 307-308 |
10 | EE | Takashi Yokota,
Masamichi Nagafuchi,
Yoshito Mekada,
Tsutomu Yoshinaga,
Kanemitsu Ootsu,
Takanobu Baba:
Real-Time Medical Diagnosis on a Multiple FPGA-based System.
FPL 2002: 1088-1091 |
9 | | Masahiro Sowa,
Ben A. Abderazek,
Soichi Shigeta,
Kirilka Nikolova,
Tsutomu Yoshinaga:
Proposal and Design of a Parallel Queue Processor Architecture (PQP).
IASTED PDCS 2002: 549-554 |
2001 |
8 | | Kanemitsu Ootsu,
Tsutomu Yoshinaga,
Takanobu Baba:
Design and Evaluation of Speculative Multi-threading with Selective Multi-Path Execution.
IPDPS 2001: 139 |
2000 |
7 | EE | Tsutomu Yoshinaga,
Masaya Hayashi,
Maki Horita,
Sayuri Nakamura,
Kanemitsu Ootsu,
Takanobu Baba:
Recover-X: An Adaptive Router with Limited Escape Channels.
ICPADS 2000: 272-279 |
1998 |
6 | EE | Tsutomu Yoshinaga,
Masaya Hayashi,
Maki Horita,
Y. Yamaguchi,
Kanemitsu Ootsu,
Takanobu Baba:
A Cost and Performance Comparison for Wormhole Routers based on HDL Designs.
ICPADS 1998: 375-382 |
1997 |
5 | | Lawrence Mutenda,
Manabu Hiyama,
Tsutomu Yoshinaga,
Takanobu Baba:
Parallel Navigation in an A-NETL Based Parallel OODBMS.
ISHPC 1997: 305-316 |
4 | EE | Takanobu Baba,
Yasushige Furuya,
Tsutomu Yoshinaga:
Event-based debugging system for a parallel object-oriented language A-NETL.
Systems and Computers in Japan 28(11): 53-63 (1997) |
1995 |
3 | | Takanobu Baba,
Tsutomu Yoshinaga,
Takahiro Furuta:
Programming and Debugging for Massively Parallelism: The Case for a Parallel Object-Oriented Language A-NETL.
OBPDC 1995: 38-58 |
1990 |
2 | EE | Takanobu Baba,
Tsutomu Yoshinaga,
Tohru Iijima,
Yoshifumi Iwamoto,
Masahiro Hamada,
Mitsuru Suzuki:
A parallel object-oriented total architecture: A-NET.
SC 1990: 276-285 |
1 | EE | Takanobu Baba,
Yoshifumi Iwamoto,
Tsutomu Yoshinaga:
A network-topology independent task allocation strategy for parallel computers.
SC 1990: 878-887 |