| 2009 |
|---|
| 9 | EE | Niti Madan,
Li Zhao,
Naveen Muralimanohar,
Aniruddha Udipi,
Rajeev Balasubramonian,
Ravishankar Iyer,
Srihari Makineni,
Donald Newell:
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.
HPCA 2009: 262-274 |
| 2008 |
|---|
| 8 | EE | Seth H. Pugsley,
Manu Awasthi,
Niti Madan,
Naveen Muralimanohar,
Rajeev Balasubramonian:
Scalable and reliable communication for hardware transactional memory.
PACT 2008: 144-154 |
| 7 | EE | Naveen Muralimanohar,
Rajeev Balasubramonian,
Norman P. Jouppi:
Architecting Efficient Interconnects for Large Caches with CACTI 6.0.
IEEE Micro 28(1): 69-79 (2008) |
| 2007 |
|---|
| 6 | EE | Naveen Muralimanohar,
Rajeev Balasubramonian:
Interconnect design considerations for large NUCA caches.
ISCA 2007: 369-380 |
| 5 | EE | Naveen Muralimanohar,
Rajeev Balasubramonian,
Norman P. Jouppi:
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.
MICRO 2007: 3-14 |
| 2006 |
|---|
| 4 | EE | Liqun Cheng,
Naveen Muralimanohar,
Karthik Ramani,
Rajeev Balasubramonian,
John B. Carter:
Interconnect-Aware Coherence Protocols for Chip Multiprocessors.
ISCA 2006: 339-351 |
| 3 | EE | Naveen Muralimanohar,
Karthik Ramani,
Rajeev Balasubramonian:
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity.
ISPASS 2006: 100-111 |
| 2 | EE | Rajeev Balasubramonian,
Naveen Muralimanohar,
Karthik Ramani,
Liqun Cheng,
John B. Carter:
Leveraging Wire Properties at the Microarchitecture Level.
IEEE Micro 26(6): 40-52 (2006) |
| 2005 |
|---|
| 1 | EE | Rajeev Balasubramonian,
Naveen Muralimanohar,
Karthik Ramani,
Venkatanand Venkatachalapathy:
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.
HPCA 2005: 28-39 |
