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Eero Aho

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2008
9EEJarno Vanne, Eero Aho, Timo D. Hämäläinen, Kimmo Kuusilinna: A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms. IEEE Trans. Circuits Syst. Video Techn. 18(4): 538-543 (2008)
8EEEero Aho, Jarno Vanne, Timo D. Hämäläinen: Configurable Data Memory for Multimedia Processing. Signal Processing Systems 50(2): 231-249 (2008)
2007
7EEEero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna: Configurable implementation of parallel memory based real-time video downscaler. Microprocessors and Microsystems 31(5): 283-292 (2007)
2006
6 Eero Aho, Jarno Vanne, Timo D. Hämäläinen: Parallel Memory Architecture for Arbitrary Stride Accesses. DDECS 2006: 65-70
5EEEero Aho, Jarno Vanne, Timo D. Hämäläinen: Parallel Memory Implementation for Arbitrary Stride Accesses. ICSAMOS 2006: 1-6
4EEJarno Vanne, Eero Aho, Timo Hämäläinen, Kimmo Kuusilinna: A High-Performance Sum of Absolute Difference Implementation for Motion Estimation. IEEE Trans. Circuits Syst. Video Techn. 16(7): 876-883 (2006)
2005
3EEEero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo Hämäläinen: Block-level parallel processing for scaling evenly divisible frames. ISCAS (2) 2005: 1134-1137
2EEEero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen: Comments on "Winscale: an image-scaling algorithm using an area pixel Model". IEEE Trans. Circuits Syst. Video Techn. 15(3): 454-455 (2005)
2002
1EEJarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen: Enhanced Configurable Parallel Memory Architecture. DSD 2002: 28-37

Coauthor Index

1Timo Hämäläinen (Timo D. Hämäläinen, Timo Sippala) [1] [2] [3] [4] [5] [6] [7] [8] [9]
2Kimmo Kuusilinna [1] [2] [3] [4] [7] [9]
3Jarno Vanne [1] [2] [3] [4] [5] [6] [7] [8] [9]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)