| 2009 |
|---|
| 60 | EE | Alex Fit-Florea,
Lun Li,
Mitchell A. Thornton,
David W. Matula:
A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k: Algorithms and Lookup Structures.
IEEE Trans. Computers 58(2): 163-174 (2009) |
| 2008 |
|---|
| 59 | EE | David W. Matula:
Foundations of Higher Radix Numeric Computation.
ISMVL 2008: 124 |
| 58 | EE | Mitchell A. Thornton,
David W. Matula,
Laura Spenner,
D. Michael Miller:
Quantum Logic Implementation of Unary Arithmetic Operations.
ISMVL 2008: 202-207 |
| 2006 |
|---|
| 57 | EE | Lun Li,
Mitchell A. Thornton,
David W. Matula:
A digit serial algorithm for the integer power operation.
ACM Great Lakes Symposium on VLSI 2006: 302-307 |
| 56 | EE | Lun Li,
Alex Fit-Florea,
Mitchell A. Thornton,
David W. Matula:
Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions.
ASAP 2006: 99-104 |
| 55 | EE | David W. Matula,
Lee D. McFearin:
A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division.
DATE 2006: 1134-1138 |
| 2005 |
|---|
| 54 | EE | Alex Fit-Florea,
David W. Matula:
Determining all pairs edge connectivity of a 4-regular graph in O(|V|).
AICCSA 2005: 15 |
| 53 | EE | David W. Matula,
Alex Fit-Florea,
Mitchell Aaron Thornton:
Table Lookup Structures for Multiplicative Inverses Modulo 2k.
IEEE Symposium on Computer Arithmetic 2005: 156-163 |
| 52 | EE | Peter Kornerup,
David W. Matula:
Single Precision Reciprocals by Multipartite Table Lookup.
IEEE Symposium on Computer Arithmetic 2005: 240-248 |
| 51 | EE | Lun Li,
Alex Fit-Florea,
Mitchell A. Thornton,
David W. Matula:
Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2k.
ISVLSI 2005: 130-135 |
| 50 | EE | Peter-Michael Seidel,
Lee D. McFearin,
David W. Matula:
Secondary Radix Recodings for Higher Radix Multipliers.
IEEE Trans. Computers 54(2): 111-123 (2005) |
| 2004 |
|---|
| 49 | EE | Alex Fit-Florea,
David W. Matula:
A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2k.
ASAP 2004: 236-246 |
| 2003 |
|---|
| 48 | EE | David W. Matula:
Computer Arithmetic - An Algorithm Engineer?s Perspective.
IEEE Symposium on Computer Arithmetic 2003: 2- |
| 47 | EE | David W. Matula,
Alex Fit-Florea:
Prescaled Integer Division.
IEEE Symposium on Computer Arithmetic 2003: 63- |
| 46 | | David W. Matula,
Lee D. McFearin:
A p×p bit fraction model of binary floating point division and extremal rounding cases.
Theor. Comput. Sci. 291(2): 159-182 (2003) |
| 45 | EE | Marc Daumas,
David W. Matula:
Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set.
VLSI Signal Processing 33(1-2): 7-18 (2003) |
| 2002 |
|---|
| 44 | EE | David W. Matula,
Alex Fit-Florea,
Lee D. McFearin:
Evaluating Products of Non Linear Functions by Indirect Bipartite Table Lookup.
ASAP 2002: 120-129 |
| 43 | EE | Mihaela Iridon,
David W. Matula:
Regular Triangulated Toroidal Graphs with Applications to Cellular and Interconnection Networks.
J. Graph Algorithms Appl. 6(4): 373-404 (2002) |
| 2001 |
|---|
| 42 | | Lee D. McFearin,
David W. Matula:
Selecting A Well Distributed Hard Case Test Suite for IEEE Standard Floating Point Division.
ICCD 2001: 89-97 |
| 41 | EE | David W. Matula:
Improved Table Lookup Algorithms for Postscaled Division.
IEEE Symposium on Computer Arithmetic 2001: 101- |
| 40 | EE | Lee D. McFearin,
David W. Matula:
Generation and Analysis of Hard to Round Cases for Binary Floating Point Division.
IEEE Symposium on Computer Arithmetic 2001: 119-127 |
| 39 | EE | Peter-Michael Seidel,
Lee D. McFearin,
David W. Matula:
Binary Multiplication Radix-32 and Radix-256.
IEEE Symposium on Computer Arithmetic 2001: 23-32 |
| 38 | | Mihaela Iridon,
David W. Matula,
Cheng Yang:
A Graph Theoretic Approach for Channel Assignment in Cellular Networks.
Wireless Networks 7(6): 567-574 (2001) |
| 2000 |
|---|
| 37 | EE | Marc Daumas,
David W. Matula:
A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with No Additional Delay.
ASAP 2000: 205-214 |
| 36 | EE | Asger Munk Nielsen,
David W. Matula,
Chung Nan Lyu,
Guy Even:
An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm.
IEEE Trans. Computers 49(1): 33-47 (2000) |
| 35 | EE | Milos D. Ercegovac,
Laurent Imbert,
David W. Matula,
Jean-Michel Muller,
Guoheng Wei:
Improving Goldschmidt Division, Square Root, and Square Root Reciprocal.
IEEE Trans. Computers 49(7): 759-763 (2000) |
| 1999 |
|---|
| 34 | EE | Hakki C. Cankaya,
David W. Matula,
Mihaela Iridon:
Performance Analysis of a Graph Model for Channel Assignment in a Cellular Network.
COMPSAC 1999: 239- |
| 33 | EE | Cristina Iordache,
David W. Matula:
On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root Reciprocal.
IEEE Symposium on Computer Arithmetic 1999: 233-240 |
| 32 | EE | Cristina Iordache,
David W. Matula:
Analysis of Reciprocal and Square Root Reciprocal Instructions in the AMD K6-2 Implementation of 3DNow!
Electr. Notes Theor. Comput. Sci. 24: (1999) |
| 31 | EE | Abbas Edalat,
David W. Matula,
Philipp Sünderhauf:
Preface.
Electr. Notes Theor. Comput. Sci. 24: (1999) |
| 1998 |
|---|
| 30 | EE | Mihaela Iridon,
David W. Matula:
Symmetric Cellular Network Embeddings on a Torus.
ICCCN 1998: 732-736 |
| 1997 |
|---|
| 29 | EE | David W. Matula,
Asger Munk Nielsen:
Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder.
IEEE Symposium on Computer Arithmetic 1997: 140-147 |
| 28 | EE | Asger Munk Nielsen,
David W. Matula,
Chung Nan Lyu,
Guy Even:
Pipelined Packet-Forwarding Floating Point: II. An Adder.
IEEE Symposium on Computer Arithmetic 1997: 148-155 |
| 27 | EE | Debjit Das Sarma,
David W. Matula:
Faithful Interpolation in Reciprocal Tables.
IEEE Symposium on Computer Arithmetic 1997: 82-91 |
| 26 | | Marc Daumas,
David W. Matula:
Validated Roundings of Dot Products by Sticky Accumulation.
IEEE Trans. Computers 46(5): 623-629 (1997) |
| 1995 |
|---|
| 25 | EE | Debjit Das Sarma,
David W. Matula:
Faithful Bipartite ROM Reciprocal Tables.
IEEE Symposium on Computer Arithmetic 1995: 17- |
| 24 | EE | Chung Nan Lyu,
David W. Matula:
Redundant Binary Booth Recoding.
IEEE Symposium on Computer Arithmetic 1995: 50- |
| 23 | EE | Peter Kornerup,
David W. Matula:
LCF: A Lexicagraphic Binary representation of the Rationals.
J. UCS 1(7): 484-503 (1995) |
| 1994 |
|---|
| 22 | | Debjit Das Sarma,
David W. Matula:
Measuring the Accuracy of ROM Reciprocal Tables.
IEEE Trans. Computers 43(8): 932-940 (1994) |
| 1993 |
|---|
| 21 | EE | W. S. Briggs,
David W. Matula:
A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latency.
IEEE Symposium on Computer Arithmetic 1993: 163-170 |
| 20 | EE | Marc Daumas,
David W. Matula:
Design of a fast validated dot product operation.
IEEE Symposium on Computer Arithmetic 1993: 62-69 |
| 19 | EE | Debjit Das Sarma,
David W. Matula:
Measuring the accuracy of ROM reciprocal tables.
IEEE Symposium on Computer Arithmetic 1993: 95-102 |
| 18 | | David W. Matula:
A Linear Time 2+epsilon Approximation Algorithm for Edge Connectivity.
SODA 1993: 500-504 |
| 1990 |
|---|
| 17 | EE | David W. Matula:
Design of a highly parallel IEEE standard floating point unit: the Cyrix 83D87 coprocessor.
SPDP 1990: 334 |
| 16 | EE | David W. Matula,
Farhad Shahrokhi:
Sparsest cuts and bottlenecks in graphs.
Discrete Applied Mathematics 27(1-2): 113-123 (1990) |
| 15 | | Peter Kornerup,
David W. Matula:
An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic.
IEEE Trans. Computers 39(8): 1106-1115 (1990) |
| 14 | EE | Farhad Shahrokhi,
David W. Matula:
The Maximum Concurrent Flow Problem
J. ACM 37(2): 318-334 (1990) |
| 1988 |
|---|
| 13 | | Peter Kornerup,
David W. Matula:
An On-Line Arithmetic Unit for Bit-Pipelined Rational Arithmetic.
J. Parallel Distrib. Comput. 5(3): 310-330 (1988) |
| 1987 |
|---|
| 12 | EE | Farhad Shahrokhi,
David W. Matula:
On solving large maximum concurrent flow problems.
ACM Conference on Computer Science 1987: 205-209 |
| 11 | | David W. Matula:
Determining Edge Connectivity in O(nm)
FOCS 1987: 249-251 |
| 10 | | David W. Matula:
Expose-and-merge exploration and the chromatic number of random graph.
Combinatorica 7(3): 275-284 (1987) |
| 1986 |
|---|
| 9 | | Jit Biswas,
David W. Matula:
Two Flow Routing Algorithms for the Maximum Concurrent-Flow Problem.
FJCC 1986: 629-636 |
| 1985 |
|---|
| 8 | | David W. Matula,
Peter Kornerup:
Finite Precision Rational Arithmetic Slash Number Systems.
IEEE Trans. Computers 34(1): 3-18 (1985) |
| 1983 |
|---|
| 7 | | Peter Kornerup,
David W. Matula:
Finite Precision Rational Arithmetic: An Arithmetic Unit.
IEEE Trans. Computers 32(4): 378-388 (1983) |
| 6 | EE | David W. Matula,
Leland L. Beck:
Smallest-Last Ordering and clustering and Graph Coloring Algorithms
J. ACM 30(3): 417-427 (1983) |
| 1982 |
|---|
| 5 | EE | David W. Matula:
Basic digit sets for radix representation.
J. ACM 29(4): 1131-1143 (1982) |
| 1979 |
|---|
| 4 | | David W. Matula,
Peter Kornerup:
An approximate rational arithmetic system with intrinsic recovery of simple fractions during expression evaluation.
EUROSAM 1979: 383-397 |
| 1978 |
|---|
| 3 | EE | David W. Matula:
k-Blocks and ultrablocks in graphs.
J. Comb. Theory, Ser. B 24(1): 1-13 (1978) |
| 1971 |
|---|
| 2 | | David W. Matula:
Significant Digits: Numerical Analysis or Numerology.
IFIP Congress (2) 1971: 1278-1283 |
| 1968 |
|---|
| 1 | EE | David W. Matula:
In-and-out conversions.
Commun. ACM 11(1): 47-50 (1968) |
