| 2008 |
|---|
| 8 | EE | Gerald R. Morris,
Viktor K. Prasanna:
A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer.
J. Parallel Distrib. Comput. 68(7): 913-921 (2008) |
| 2007 |
|---|
| 7 | EE | Gerald R. Morris,
Viktor K. Prasanna:
Sparse Matrix Computations on Reconfigurable Hardware.
IEEE Computer 40(3): 58-64 (2007) |
| 6 | EE | Ling Zhuo,
Gerald R. Morris,
Viktor K. Prasanna:
High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs.
IEEE Trans. Parallel Distrib. Syst. 18(10): 1377-1392 (2007) |
| 2006 |
|---|
| 5 | EE | Gerald R. Morris,
Viktor K. Prasanna,
Richard D. Anderson:
An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets.
ASAP 2006: 323-330 |
| 4 | EE | Gerald R. Morris,
Viktor K. Prasanna,
Richard D. Anderson:
A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer.
FCCM 2006: 3-12 |
| 2005 |
|---|
| 3 | EE | Gerald R. Morris,
Ling Zhuo,
Viktor K. Prasanna:
High-Performance FPGA-Based General Reduction Methods.
FCCM 2005: 323-324 |
| 2 | EE | Ling Zhuo,
Gerald R. Morris,
Viktor K. Prasanna:
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores.
IPDPS 2005 |
| 1 | EE | Gerald R. Morris,
Viktor K. Prasanna:
An FPGA-Based Floating-Point Jacobi Iterative Solver.
ISPAN 2005: 420-427 |
