| 1999 |
|---|
| 5 | EE | Hsiao-Pin Su,
Allen C.-H. Wu,
Youn-Long Lin:
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning.
DAC 1999: 262-267 |
| 4 | EE | Hsiao-Pin Su,
Allen C.-H. Wu,
Youn-Long Lin:
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 475-483 (1999) |
| 1998 |
|---|
| 3 | EE | Tzu-Chieh Tien,
Hsiao-Pin Su,
Yu-Wen Tsay,
Yih-Chih Chou,
Youn-Long Lin:
Integrating logic retiming and register placement.
ICCAD 1998: 136-139 |
| 2 | EE | Hsiao-Pin Su,
Allen C.-H. Wu,
Youn-Long Lin:
Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy.
ISPD 1998: 12-17 |
| 1997 |
|---|
| 1 | EE | Hsiao-Pin Su,
Youn-Long Lin:
A phase assignment method for virtual-wire-based hardware emulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 776-783 (1997) |
