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Cher-Shiung Tsai

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2006
6EEDong-Shong Liang, Cheng-Chi Tai, Kwang-Jow Gan, Cher-Shiung Tsai, Yaw-Hwang Chen: Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process. APCCAS 2006: 1325-1328
5EEKwang-Jow Gan, Dong-Shong Liang, Cher-Shiung Tsai, Yaw-Hwang Chen, Chun-Ming Wen: Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process. APCCAS 2006: 1476-1479
4EEDong-Shong Liang, Yaw-Hwang Chen, Chun-Min Wen, Chun-Da Tu, Kwang-Jow Gan, Cher-Shiung Tsai: The Design of MOS-NDR-Based Cellular Neural Network. IJCNN 2006: 1033-1035
2005
3EEDong-Shong Liang, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su: Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits. IWSOC 2005: 372-375
2EEKwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen: Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process. IWSOC 2005: 392-395
1EEDong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang: Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits. IWSOC 2005: 78-81

Coauthor Index

1Chi-Pin Chen [1] [2]
2Yaw-Hwang Chen [1] [2] [3] [4] [5] [6]
3Feng-Chang Chiang [1] [2] [3]
4Kwang-Jow Gan [1] [2] [3] [4] [5] [6]
5Chung-Chih Hsiao [1] [2] [3]
6Shun-Huo Kuo [1] [2] [3]
7Dong-Shong Liang [1] [2] [3] [4] [5] [6]
8Long-Xian Su [1] [3]
9Cheng-Chi Tai [6]
10Chun-Da Tu [4]
11Shih-Yu Wang [1] [2] [3]
12Chun-Min Wen [4]
13Chun-Ming Wen [5]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)