| 2006 |
|---|
| 6 | EE | Dong-Shong Liang,
Cheng-Chi Tai,
Kwang-Jow Gan,
Cher-Shiung Tsai,
Yaw-Hwang Chen:
Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process.
APCCAS 2006: 1325-1328 |
| 5 | EE | Kwang-Jow Gan,
Dong-Shong Liang,
Cher-Shiung Tsai,
Yaw-Hwang Chen,
Chun-Ming Wen:
Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process.
APCCAS 2006: 1476-1479 |
| 4 | EE | Dong-Shong Liang,
Yaw-Hwang Chen,
Chun-Min Wen,
Chun-Da Tu,
Kwang-Jow Gan,
Cher-Shiung Tsai:
The Design of MOS-NDR-Based Cellular Neural Network.
IJCNN 2006: 1033-1035 |
| 2005 |
|---|
| 3 | EE | Dong-Shong Liang,
Kwang-Jow Gan,
Chung-Chih Hsiao,
Cher-Shiung Tsai,
Yaw-Hwang Chen,
Shih-Yu Wang,
Shun-Huo Kuo,
Feng-Chang Chiang,
Long-Xian Su:
Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits.
IWSOC 2005: 372-375 |
| 2 | EE | Kwang-Jow Gan,
Dong-Shong Liang,
Chung-Chih Hsiao,
Shih-Yu Wang,
Feng-Chang Chiang,
Cher-Shiung Tsai,
Yaw-Hwang Chen,
Shun-Huo Kuo,
Chi-Pin Chen:
Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process.
IWSOC 2005: 392-395 |
| 1 | EE | Dong-Shong Liang,
Kwang-Jow Gan,
Long-Xian Su,
Chi-Pin Chen,
Chung-Chih Hsiao,
Cher-Shiung Tsai,
Yaw-Hwang Chen,
Shih-Yu Wang,
Shun-Huo Kuo,
Feng-Chang Chiang:
Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits.
IWSOC 2005: 78-81 |
