| |
| 2005 | ||
|---|---|---|
| 3 | EE | Ki-Bog Kim, Chi-Ho Lin: An Optimal ILP Model for Delay Time to Minimize Peak Power and Area. IWSOC 2005: 358-362 |
| 2003 | ||
| 2 | EE | Chang Hee Pyoun, Chi-Ho Lin, Hi-Seok Kim, Jong Wha Chong: The Efficient Bus Arbitration Scheme in SoC Environment. IWSOC 2003: 311-315 |
| 2001 | ||
| 1 | EE | Jae-Jin Kim, Hi-Seok Kim, Chi-Ho Lin: A new techology mapping for CPLD under the time constraint. ASP-DAC 2001: 235-238 |
| 1 | Jong Wha Chong | [2] |
| 2 | Hi-Seok Kim | [1] [2] |
| 3 | Jae-Jin Kim | [1] |
| 4 | Ki-Bog Kim | [3] |
| 5 | Chang Hee Pyoun | [2] |