Hung Tien Bui

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7EEHung Tien Bui: Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis. ISCAS 2008: 3422-3425
6EEBill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria: A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. ISCAS 2007: 633-636
5EEHung Tien Bui, Yvon Savaria: High speed differential pulse-width control loop based on frequency-to-voltage converters. ACM Great Lakes Symposium on VLSI 2006: 53-56
4EEHung Tien Bui: Dual-Path and Diode-Tracking Active Inductors for MCML Gates. CCECE 2006: 1060-1063
3EEHung Tien Bui, Yvon Savaria: A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs. IWSOC 2005: 557-562
2 Hung Tien Bui, Yvon Savaria: Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. ISCAS (4) 2004: 369-372
1EEHung Tien Bui, Yvon Savaria: 10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. IWSOC 2004: 115-118

Coauthor Index

1François R. Boyer [6]
2Bill Pontikakis [6]
3Yvon Savaria [1] [2] [3] [5] [6]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)