| 2008 |
|---|
| 7 | EE | Hung Tien Bui:
Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis.
ISCAS 2008: 3422-3425 |
| 2007 |
|---|
| 6 | EE | Bill Pontikakis,
Hung Tien Bui,
François R. Boyer,
Yvon Savaria:
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.
ISCAS 2007: 633-636 |
| 2006 |
|---|
| 5 | EE | Hung Tien Bui,
Yvon Savaria:
High speed differential pulse-width control loop based on frequency-to-voltage converters.
ACM Great Lakes Symposium on VLSI 2006: 53-56 |
| 4 | EE | Hung Tien Bui:
Dual-Path and Diode-Tracking Active Inductors for MCML Gates.
CCECE 2006: 1060-1063 |
| 2005 |
|---|
| 3 | EE | Hung Tien Bui,
Yvon Savaria:
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs.
IWSOC 2005: 557-562 |
| 2004 |
|---|
| 2 | | Hung Tien Bui,
Yvon Savaria:
Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector.
ISCAS (4) 2004: 369-372 |
| 1 | EE | Hung Tien Bui,
Yvon Savaria:
10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS.
IWSOC 2004: 115-118 |
