| 2007 |
|---|
| 6 | EE | Chao-Tung Yang,
Shih-Yu Wang,
Chun-Pin Fu:
A Dynamic Adjustment Strategy for File Transformation in Data Grids.
NPC 2007: 61-70 |
| 5 | EE | Chao-Tung Yang,
I-Hsien Yang,
Kuan-Ching Li,
Shih-Yu Wang:
Improvements on dynamic adjustment mechanism in co-allocation data grid environments.
The Journal of Supercomputing 40(3): 269-280 (2007) |
| 2006 |
|---|
| 4 | EE | Chao-Tung Yang,
I-Hsien Yang,
Chun-Hsiang Chen,
Shih-Yu Wang:
Implementation of a dynamic adjustment mechanism with efficient replica selection in data grid environments.
SAC 2006: 797-804 |
| 2005 |
|---|
| 3 | EE | Dong-Shong Liang,
Kwang-Jow Gan,
Chung-Chih Hsiao,
Cher-Shiung Tsai,
Yaw-Hwang Chen,
Shih-Yu Wang,
Shun-Huo Kuo,
Feng-Chang Chiang,
Long-Xian Su:
Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits.
IWSOC 2005: 372-375 |
| 2 | EE | Kwang-Jow Gan,
Dong-Shong Liang,
Chung-Chih Hsiao,
Shih-Yu Wang,
Feng-Chang Chiang,
Cher-Shiung Tsai,
Yaw-Hwang Chen,
Shun-Huo Kuo,
Chi-Pin Chen:
Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process.
IWSOC 2005: 392-395 |
| 1 | EE | Dong-Shong Liang,
Kwang-Jow Gan,
Long-Xian Su,
Chi-Pin Chen,
Chung-Chih Hsiao,
Cher-Shiung Tsai,
Yaw-Hwang Chen,
Shih-Yu Wang,
Shun-Huo Kuo,
Feng-Chang Chiang:
Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits.
IWSOC 2005: 78-81 |
