| 2008 |
|---|
| 7 | EE | Miao Li,
Tad Kwasniewski,
Shoujun Wang:
A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops.
ISCAS 2008: 2358-2361 |
| 2006 |
|---|
| 6 | EE | Miao Li,
Tad A. Kwasniewski,
Shoujun Wang:
A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane Applications.
APCCAS 2006: 1039-1042 |
| 5 | EE | Wm. Bereza,
Yuming Tao,
Shoujun Wang,
Tad A. Kwasniewski,
Rakesh H. Patel:
PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations.
DAC 2006: 1013-1016 |
| 4 | EE | Miao Li,
Wenjie Huang,
Tad A. Kwasniewski,
Shoujun Wang:
A 0.18µm CMOS clock and data recovery circuit with extended operation range.
ISCAS 2006 |
| 2005 |
|---|
| 3 | EE | Miao Li,
Tad A. Kwasniewski,
Shoujun Wang,
Yuming Tao:
A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology.
ASP-DAC 2005: 679-682 |
| 2 | EE | Miao Li,
Wenjie Huang,
Tad A. Kwasniewski,
Shoujun Wang:
A 0.18µm CMOS transceiver design for high-speed backplane data communications.
ISCAS (2) 2005: 1158-1161 |
| 1 | EE | Miao Li,
Peter Noel,
Tad A. Kwasniewski,
Shoujun Wang:
Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications.
IWSOC 2005: 500-502 |
