| 2009 |
|---|
| 64 | EE | André Seznec,
Joel S. Emer,
Michael F. P. O'Boyle,
Margaret Martonosi,
Theo Ungerer:
High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings
Springer 2009 |
| 63 | EE | Hans Vandierendonck,
André Seznec:
Fetch Gating Control through Speculative Instruction Window Weighting.
T. HiPEAC 2: 128-148 (2009) |
| 2008 |
|---|
| 62 | EE | Hans Vandierendonck,
André Seznec:
Speculative return address stack management revisited.
TACO 5(3): (2008) |
| 2007 |
|---|
| 61 | EE | Thomas Piquet,
Olivier Rochecouste,
André Seznec:
Exploiting Single-Usage for Effective Memory Management.
Asia-Pacific Computer Systems Architecture Conference 2007: 90-101 |
| 60 | EE | Hans Vandierendonck,
André Seznec:
Fetch Gating Control Through Speculative Instruction Window Weighting.
HiPEAC 2007: 120-135 |
| 59 | EE | Koen De Bosschere,
Wayne Luk,
Xavier Martorell,
Nacho Navarro,
Michael F. P. O'Boyle,
Dionisios N. Pnevmatikatos,
Alex Ramírez,
Pascal Sainrat,
André Seznec,
Per Stenström,
Olivier Temam:
High-Performance Embedded Architecture and Compilation Roadmap.
T. HiPEAC 1: 5-29 (2007) |
| 58 | EE | Pierre Michaud,
André Seznec,
Damien Fetis,
Yiannakis Sazeides,
Theofanis Constantinou:
A study of thread migration in temperature-constrained multicores.
TACO 4(2): (2007) |
| 2006 |
|---|
| 57 | EE | Olivier Rochecouste,
Gilles Pokam,
André Seznec:
A case for a complexity-effective, width-partitioned microarchitecture.
TACO 3(3): 295-326 (2006) |
| 2005 |
|---|
| 56 | EE | André Seznec:
Analysis of the O-GEometric History Length Branch Predictor.
ISCA 2005: 394-405 |
| 55 | EE | André Seznec,
Roger Espasa:
Conflict-Free Accesses to Strided Vectors on a Banked Cache.
IEEE Trans. Computers 54(7): 913-196 (2005) |
| 54 | EE | Julio César Hernández Castro,
José María Sierra,
André Seznec,
Antonio Izquierdo,
Arturo Ribagorda:
The strict avalanche criterion randomness test.
Mathematics and Computers in Simulation 68(1): 1-7 (2005) |
| 53 | EE | Theofanis Constantinou,
Yiannakis Sazeides,
Pierre Michaud,
Damien Fetis,
André Seznec:
Performance implications of single thread migration on a chip multi-core.
SIGARCH Computer Architecture News 33(4): 80-91 (2005) |
| 2004 |
|---|
| 52 | | Paul Feautrier,
James Goodman,
André Seznec:
Proceedings of the 18th Annual International Conference on Supercomputing, ICS 2004, Saint Malo, France, June 26 - July 01, 2004
ACM 2004 |
| 51 | EE | Kemal Ebcioglu,
Wolfgang Karl,
André Seznec,
Marco Aldinucci:
Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism.
Euro-Par 2004: 506 |
| 50 | EE | Julio César Hernández Castro,
José María Sierra,
André Seznec:
The SAC Test: A New Randomness Test, with Some Applications to PRNG Analysis.
ICCSA (1) 2004: 960-967 |
| 49 | EE | Gilles Pokam,
Olivier Rochecouste,
André Seznec,
François Bodin:
Speculative software management of datapath-width for energy optimization.
LCTES 2004: 78-87 |
| 48 | EE | Amaury Darsch,
André Seznec:
IATO: A Flexible EPIC Simulation Environment.
SBAC-PAD 2004: 58-65 |
| 47 | EE | André Seznec:
Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB.
IEEE Trans. Computers 53(7): 924-927 (2004) |
| 46 | | Romain Dolbeau,
André Seznec:
CASH: Revisiting Hardware Sharing in Single-Chip Parallel Processors.
J. Instruction-Level Parallelism 6: (2004) |
| 2003 |
|---|
| 45 | EE | André Seznec,
Antony Fraboulet:
Effective ahead Pipelining of Instruction Block Address Generation.
ISCA 2003: 241-252 |
| 44 | EE | André Seznec,
Nicolas Sendrier:
HAVEGE: A user-level software heuristic for generating empirically strong random numbers.
ACM Trans. Model. Comput. Simul. 13(4): 334-346 (2003) |
| 2002 |
|---|
| 43 | EE | Roger Espasa,
Federico Ardanaz,
Julio Gago,
Roger Gramunt,
Isaac Hernandez,
Toni Juan,
Joel S. Emer,
Stephen Felix,
P. Geoffrey Lowney,
Matthew Mattina,
André Seznec:
Tarantula: A Vector Extension to the Alpha Architecture.
ISCA 2002: 281- |
| 42 | EE | André Seznec,
Stephen Felix,
Venkata Krishnan,
Yiannakis Sazeides:
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor.
ISCA 2002: 295-306 |
| 41 | EE | André Seznec,
Eric Toullec,
Olivier Rochecouste:
Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors.
MICRO 2002: 383-394 |
| 2001 |
|---|
| 40 | EE | Eduard Ayguadé,
Fredrik Dahlgren,
Christine Eisenbeis,
Roger Espasa,
Guang R. Gao,
Henk L. Muller,
Rizos Sakellariou,
André Seznec:
Topic 08+13: Instruction-Level Parallelism and Computer Architecture.
Euro-Par 2001: 385 |
| 39 | EE | Pierre Michaud,
André Seznec:
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors.
HPCA 2001: 27-36 |
| 38 | | Kun Luo,
Manoj Franklin,
Shubhendu S. Mukherjee,
André Seznec:
Boosting SMT Performance by Speculation Control.
IPDPS 2001: 2 |
| 37 | | Pierre Michaud,
André Seznec,
Stéphan Jourdan:
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors.
International Journal of Parallel Programming 29(1): 35-58 (2001) |
| 2000 |
|---|
| 36 | EE | Thierry Lafage,
André Seznec:
Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note).
Euro-Par 2000: 178-182 |
| 35 | | Erven Rohou,
François Bodin,
Christine Eisenbeis,
André Seznec:
Handling Global Constraints in Compiler Strategy.
International Journal of Parallel Programming 28(4): 325-345 (2000) |
| 1999 |
|---|
| 34 | EE | Michel Barreteau,
François Bodin,
Zbigniew Chamski,
Henri-Pierre Charles,
Christine Eisenbeis,
John R. Gurd,
Jan Hoogerbrugge,
Ping Hu,
William Jalby,
Toru Kisuki,
Peter M. W. Knijnenburg,
Paul van der Mark,
Andy Nisbet,
Michael F. P. O'Boyle,
Erven Rohou,
André Seznec,
Elena Stöhr,
Menno Treffers,
Harry A. G. Wijshoff:
OCEANS - Optimising Compilers for Embedded Applications.
Euro-Par 1999: 1171-1175 |
| 33 | EE | Thierry Lafage,
André Seznec,
Erven Rohou,
François Bodin:
Code Cloning Tracing: A ``Pay per Trace'' Approach.
Euro-Par 1999: 1265-1268 |
| 32 | EE | Sébastien Hily,
André Seznec:
Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading.
HPCA 1999: 64- |
| 31 | EE | Pierre Michaud,
André Seznec,
Stéphan Jourdan:
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.
IEEE PACT 1999: 2-10 |
| 1998 |
|---|
| 30 | EE | Michel Barreteau,
François Bodin,
Peter Brinkhaus,
Zbigniew Chamski,
Henri-Pierre Charles,
Christine Eisenbeis,
John R. Gurd,
Jan Hoogerbrugge,
Ping Hu,
William Jalby,
Peter M. W. Knijnenburg,
Michael F. P. O'Boyle,
Erven Rohou,
Rizos Sakellariou,
André Seznec,
Elena Stöhr,
Menno Treffers,
Harry A. G. Wijshoff:
OCEANS: Optimising Compilers for Embedded Applications.
Euro-Par 1998: 1123-1130 |
| 29 | EE | D. N. Truong,
François Bodin,
André Seznec:
Improving Cache Behavior of Dynamically Allocated Data Structures.
IEEE PACT 1998: 322- |
| 1997 |
|---|
| 28 | | Bas Aarts,
Michel Barreteau,
François Bodin,
Peter Brinkhaus,
Zbigniew Chamski,
Henri-Pierre Charles,
Christine Eisenbeis,
John R. Gurd,
Jan Hoogerbrugge,
Ping Hu,
William Jalby,
Peter M. W. Knijnenburg,
Michael F. P. O'Boyle,
Erven Rohou,
Rizos Sakellariou,
Henk Schepers,
André Seznec,
Elena Stöhr,
Marco Verhoeven,
Harry A. G. Wijshoff:
OCEANS: Optimizing Compilers for Embedded Applications.
Euro-Par 1997: 1351-1356 |
| 27 | EE | Pierre Michaud,
André Seznec,
Richard Uhlig:
Trading Conflict and Capacity Aliasing in Conditional Branch Predictors.
ISCA 1997: 292-303 |
| 26 | | André Seznec:
Decoupled Sectored Caches.
IEEE Trans. Computers 46(2): 210-215 (1997) |
| 25 | | François Bodin,
André Seznec:
Skewed Associativity Improves Program Performance and Enhances Predictability.
IEEE Trans. Computers 46(5): 530-544 (1997) |
| 1996 |
|---|
| 24 | | André Seznec,
Stéphan Jourdan,
Pascal Sainrat,
Pierre Michaud:
Multiple-Block Ahead Branch Predictors.
ASPLOS 1996: 116-127 |
| 23 | EE | André Seznec:
Don't Use the Page Number, But a Pointer To It.
ISCA 1996: 104-113 |
| 1995 |
|---|
| 22 | | André Seznec:
DASC Cache.
HPCA 1995: 134-143 |
| 21 | EE | François Bodin,
André Seznec:
Skewed Associativity Enhances Performance Predictability.
ISCA 1995: 265-274 |
| 20 | | André Seznec,
Jacques Lenfant:
Odd Memory Systems: A New Approach.
J. Parallel Distrib. Comput. 26(2): 248-256 (1995) |
| 19 | | Nathalie Drach,
Alain Gefflaut,
Philippe Joubert,
André Seznec:
About Cache Associativity in Low-Cost Shared Memory Multi-Microprocessors.
Parallel Processing Letters 5: 475-487 (1995) |
| 1994 |
|---|
| 18 | | André Seznec:
Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio.
ISCA 1994: 384-393 |
| 17 | EE | André Seznec,
Jacques Lenfant:
Interleaved Parallel Schemes.
IEEE Trans. Parallel Distrib. Syst. 5(12): 1329-1334 (1994) |
| 1993 |
|---|
| 16 | | André Seznec:
About Set and Skewed Associativity on Second-Level Caches.
ICCD 1993: 40-43 |
| 15 | | Nathalie Drach,
André Seznec:
Semi-Unified Caches.
ICPP 1993: 25-28 |
| 14 | | André Seznec:
A Case for Two-Way Skewed-Associative Caches.
ISCA 1993: 169-178 |
| 13 | | André Seznec,
Jacques Lenfant:
Odd Memory Systems May be Quite Interesting.
ISCA 1993: 341-350 |
| 12 | EE | Nathalie Drach,
André Seznec:
MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines.
MICRO 1993: 193-201 |
| 11 | | André Seznec,
François Bodin:
Skewed-associative Caches.
PARLE 1993: 304-316 |
| 1992 |
|---|
| 10 | | André Seznec,
Jacques Lenfant:
Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers.
ISCA 1992: 246-255 |
| 9 | EE | André Seznec,
Karl Courtel:
Controlling and sequencing a heavily pipelined floating-point operator.
MICRO 1992: 111-114 |
| 1989 |
|---|
| 8 | EE | Yvon Jégou,
André Seznec:
A asynchronous buffering network for tightly coupled multiprocessors.
ICS 1989: 331-340 |
| 1988 |
|---|
| 7 | EE | André Seznec,
Yvon Jégou:
Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cache.
ICS 1988: 611-620 |
| 6 | | André Seznec,
Yvon Jégou:
Synchronizing Processors Through Memory Requests in a Tightly Coupled Multiprocessor.
ISCA 1988: 393-400 |
| 1987 |
|---|
| 5 | | André Seznec,
Yvon Jégou:
Optimizing Memory Throughput In a Tightly Coupled Multiprocessor.
ICPP 1987: 344-346 |
| 4 | | André Seznec:
A New Interconnection Network for SIMD Computers: The Sigma Network.
IEEE Trans. Computers 36(7): 794-801 (1987) |
| 1986 |
|---|
| 3 | | Yvon Jégou,
André Seznec:
Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments.
ICPP 1986: 487-494 |
| 2 | | André Seznec:
An Efficient Routing Control Unit for the SIGMA Network E(4).
ISCA 1986: 158-168 |
| 1 | | Yvon Jégou,
André Seznec:
Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments.
J. Parallel Distrib. Comput. 3(4): 508-526 (1986) |
