| |
| 2007 | ||
|---|---|---|
| 4 | EE | Vineet Wason, Rajeev Murgai, William W. Walker: An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. VLSI Design 2007: 271-277 |
| 2005 | ||
| 3 | EE | Vineet Wason, Kaustav Banerjee: A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations. ISLPED 2005: 131-136 |
| 2004 | ||
| 2 | EE | Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee: Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. DAC 2004: 884-887 |
| 1 | EE | Songqing Zhang, Vineet Wason, Kaustav Banerjee: A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. ISLPED 2004: 156-161 |
| 1 | Kaustav Banerjee | [1] [2] [3] |
| 2 | Anirban Basu | [2] |
| 3 | Sheng-Chih Lin | [2] |
| 4 | Amit Mehrotra | [2] |
| 5 | Rajeev Murgai | [4] |
| 6 | William W. Walker | [4] |
| 7 | Songqing Zhang | [1] |