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Vineet Wason

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2007
4EEVineet Wason, Rajeev Murgai, William W. Walker: An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. VLSI Design 2007: 271-277
2005
3EEVineet Wason, Kaustav Banerjee: A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations. ISLPED 2005: 131-136
2004
2EEAnirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee: Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. DAC 2004: 884-887
1EESongqing Zhang, Vineet Wason, Kaustav Banerjee: A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. ISLPED 2004: 156-161

Coauthor Index

1Kaustav Banerjee [1] [2] [3]
2Anirban Basu [2]
3Sheng-Chih Lin [2]
4Amit Mehrotra [2]
5Rajeev Murgai [4]
6William W. Walker [4]
7Songqing Zhang [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)