2008 | ||
---|---|---|
2 | EE | Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang: A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. MEMOCODE 2008: 79-88 |
2002 | ||
1 | EE | Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton: Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. ACM Great Lakes Symposium on VLSI 2002: 1-6 |
1 | Dan Bailey | [1] |
2 | David Bertucci | [1] |
3 | Gabriel P. Bischoff | [1] |
4 | Daniel E. Dever | [1] |
5 | Mike Gowan | [1] |
6 | Joel Grodstein | [1] |
7 | Steve Haynal | [2] |
8 | Timothy Kam | [2] |
9 | Michael Kishinevsky | [2] |
10 | Roy Lane | [1] |
11 | Brian Lilly | [1] |
12 | Sue Lowell | [1] |
13 | Shannon V. Morton | [1] |
14 | Krishna Nagalla | [1] |
15 | Rachid Rayess | [1] |
16 | Rahul Shah | [1] |
17 | Linda Shattuck | [1] |
18 | Tad Truex | [1] |
19 | Xinning Wang | [2] |
20 | Shi-Huang Yin | [1] |