Formal Methods in System Design, Volume 9

Volume 9, Number 1/2, August 1996

Kurt Jensen: Condensed State Spaces for Symmetrical Coloured Petri Nets. 7-40 BibTeX
C. Norris Ip, David L. Dill: Better Verification Through Symmetry. 41-75 BibTeX
Edmund M. Clarke, Somesh Jha, Reinhard Enders, Thomas Filkorn: Exploiting Symmetry in Temporal Logic Model Checking. 77-104 BibTeX
E. Allen Emerson, A. Prasad Sistla: Symmetry and Model Checking. 105-131 BibTeX

Alexandre Yakovlev, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: A Unified Signal Transition Graph Model for Asynchronous Control Circuit Synthesis. 139-188 BibTeX
Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Marta Pietkiewicz-Koutny: On the Models for Asynchronous Circuit Behaviour with OR Causality. 189-233 BibTeX
Leo Marcus: The Incorporation of Testing into Formal Verification: Direct, Modular, and Hierarchical Correctness Degrees. 235-261 BibTeX
Tommaso Bolognesi: Regrouping Parallel Processes. 263-302 BibTeX