2005 |
11 | EE | Nicolae Savoiu,
Sandeep K. Shukla,
Rajesh K. Gupta:
Improving SystemC simulation through Petri net reductions.
MEMOCODE 2005: 131-140 |
10 | EE | Nick Savoiu:
MTP: A Petri Net-Based Framework for the Analysis and Transformation of SystemC Designs.
SCOPES 2005: 99-108 |
2004 |
9 | EE | Sumit Gupta,
Nicolae Savoiu,
Nikil D. Dutt,
Rajesh K. Gupta,
Alexandru Nicolau:
Using global code motions to improve the quality of results for high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 302-312 (2004) |
2002 |
8 | EE | Sumit Gupta,
Nick Savoiu,
Nikil D. Dutt,
Rajesh K. Gupta,
Alexandru Nicolau,
Timothy Kam,
Michael Kishinevsky,
Shai Rotem:
Coordinated transformations for high-level synthesis of high performance microprocessor blocks.
DAC 2002: 898-903 |
7 | EE | Nick Savoiu,
Sandeep K. Shukla,
Rajesh K. Gupta:
Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation.
DATE 2002: 875-883 |
6 | EE | Rajesh K. Gupta,
Sandeep K. Shukla,
Nick Savoiu:
Efficient Simulation of Synthesis-Oriented System Level Designs.
ISSS 2002: 168-173 |
5 | EE | Alexandru Nicolau,
Nikil D. Dutt,
Rajesh Gupta,
Nick Savoiu,
Mehrdad Reshadi,
Sumit Gupta:
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis.
ISSS 2002: 261-266 |
4 | | Nick Savoiu,
Sandeep K. Shukla,
Rajesh K. Gupta:
Concurrency in System Level Design: Conflict Between Simulation and Synthesis Goals.
IWLS 2002: 407-411 |
2001 |
3 | EE | Sumit Gupta,
Nick Savoiu,
Sunwoo Kim,
Nikil D. Dutt,
Rajesh K. Gupta,
Alexandru Nicolau:
Speculation Techniques for High Level Synthesis of Control Intensive Designs.
DAC 2001: 269-272 |
2 | | Sumit Gupta,
Nick Savoiu,
Nikil D. Dutt,
Rajesh K. Gupta,
Alexandru Nicolau:
Conditional speculation and its effects on performance and area for high-level snthesis.
ISSS 2001: 171-176 |
1999 |
1 | EE | Asheesh Khare,
Nicolae Savoiu,
Ashok Halambi,
Peter Grun,
Nikil D. Dutt,
Alexandru Nicolau:
V-SAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration.
EUROMICRO 1999: 1196-1203 |