| |
| 2000 | ||
|---|---|---|
| 2 | EE | Andrés D. García, Jean-Luc Danger, Wayne P. Burleson: Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. FPGA 2000: 220 |
| 1999 | ||
| 1 | Andrés D. García, Wayne P. Burleson, Jean-Luc Danger: Power Modelling in Field Programmable Gate Arrays (FPGA). FPL 1999: 396-404 | |
| 1 | Wayne P. Burleson (Wayne Burleson) | [1] [2] |
| 2 | Jean-Luc Danger | [1] [2] |