| 2007 |
|---|
| 8 | | Michaela Amoo,
Clay Gloster:
FPGA Implementation of an Analytical Design Method for A Cycle-Optimal 2D-DCT/IDCT.
ERSA 2007: 131-137 |
| 7 | EE | Wanda Gay,
Clay S. Gloster Jr.:
A Configurable Processor Synthesis System.
FCCM 2007: 331-332 |
| 2006 |
|---|
| 6 | EE | Clay Gloster,
Wanda Gay,
Michaela Amoo,
Mohamed Chouikha:
Optimizing the Design of a Configurable Digital Signal Processor for Accelerated Execution of the 2-D Discrete Cosine Transform.
HICSS 2006 |
| 2000 |
|---|
| 5 | EE | Winser E. Alexander,
Douglas S. Reeves,
Clay S. Gloster Jr.:
Parallel image processin gwith the block data paralel architecture.
IBM Journal of Research and Development 44(5): 681-702 (2000) |
| 1998 |
|---|
| 4 | EE | Marco A. Figueiredo,
Clay Gloster:
Implementation of a Probabilistic Neural Network for Multi-spectral Image Classification on an FPGA based Custom Computing Machine.
SBRN 1998: 174-179 |
| 1995 |
|---|
| 3 | EE | Clay Gloster,
Franc Brglez:
Partial scan selection for user-specified fault coverage.
EURO-DAC 1995: 111-116 |
| 1989 |
|---|
| 2 | | Franc Brglez,
Gershon Kedem,
Clay Gloster:
Hardware-Based Weighted Random Pattern Generation for Boundary Scan.
ITC 1989: 264-274 |
| 1988 |
|---|
| 1 | | Clay Gloster,
Franc Brglez:
Boundary Scan with Cellular-Based Built-In Self-Test.
ITC 1988: 138-145 |
