Zhichun Zhu

2008
14	EE	Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu: Memory Access Scheduling Schemes for Systems with Multi-Core Processors. ICPP 2008: 406-413
13	EE	Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, Zhichun Zhu: Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. MICRO 2008: 210-221
12	EE	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Eugene Gorbatov, Howard David, Zhao Zhang: Software thermal management of dram memory for multicore systems. SIGMETRICS 2008: 337-348
2007
11	EE	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang: Thermal modeling and management of DRAM memory systems. ISCA 2007: 312-322
10	EE	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang, Howard David: DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. ISPASS 2007: 94-104
2005
9	EE	Zhichun Zhu, Zhao Zhang: A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. HPCA 2005: 213-224
8	EE	Zhichun Zhu, Xiaodong Zhang: Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption. IEEE Micro 25(4): 10-19 (2005)
2004
7	EE	Zhao Zhang, Zhichun Zhu, Xiaodong Zhang: Design and Optimization of Large Size and Low Overhead Off-Chip Caches. IEEE Trans. Computers 53(7): 843-855 (2004)
2002
6	EE	Zhichun Zhu, Zhao Zhang, Xiaodong Zhang: Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. HPCA 2002: 107-116
5	EE	Zhichun Zhu, Xiaodong Zhang: Access-Mode Predictions for Low-Power Cache Design. IEEE Micro 22(2): 58-71 (2002)
2001
4	EE	Zhao Zhang, Zhichun Zhu, Xiaodong Zhang: Cached DRAM for ILP Processor Memory Access Latency Reduction. IEEE Micro 21(4): 22-32 (2001)
3	EE	Zhao Zhang, Zhichun Zhu, Xiaodong Zhang: Breaking Address Mapping Symmetry at Multi-levels of Memory Heirarchy to Reduce DRAM Row-buffer Conflicts. J. Instruction-Level Parallelism 3: (2001)
2000
2	EE	Zhao Zhang, Zhichun Zhu, Xiaodong Zhang: A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. MICRO 2000: 32-41
1	EE	Xing Du, Xiaodong Zhang, Zhichun Zhu: Memory Hierarchy Considerations for Cost-Effective Cluster Computing. IEEE Trans. Computers 49(9): 915-933 (2000)

Coauthor Index

1	Howard David	[10] [11] [12] [13]
2	Xing Du	[1]
3	Eugene Gorbatov	[12] [13]
4	Jiang Lin	[10] [11] [12] [13] [14]
5	Xiaodong Zhang	[1] [2] [3] [4] [5] [6] [7] [8]
6	Zhao Zhang	[2] [3] [4] [6] [7] [9] [10] [11] [12] [13] [14]
7	Hongzhong Zheng	[10] [11] [12] [13] [14]