Roy Ju, Dz-Ching Ju
List of publications from the DBLP Bibliography Server - FAQ
2007 | ||
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40 | EE | Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-Ching Ju: A Throughput-Driven Task Creation and Mapping for Network Processors. HiPEAC 2007: 227-241 |
39 | EE | Gilberto Contreras, Margaret Martonosi, Jinzhang Peng, Guei-Yuan Lueh, Roy Ju: The XTREM power and performance simulator for the Intel XScale core: Design and experiences. ACM Trans. Embedded Comput. Syst. 6(1): (2007) |
2006 | ||
38 | EE | Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai: Recovery code generation for general speculative optimizations. TACO 3(1): 67-89 (2006) |
2005 | ||
37 | EE | Tao Liu, Xiao-Feng Li, Lixia Liu, Chengyong Wu, Roy Ju: Optimizing Packet Accesses for a Domain Specific Language on Network Processors. LCPC 2005: 47-61 |
36 | Chen Yang, Yongjian Chen, Xiong Fu, Chu-Cheow Lim, Roy Ju: POV-Ray Parallelization and Optimization: An Experience Report. PDPTA 2005: 997-1003 | |
35 | EE | Michael K. Chen, Xiao-Feng Li, Ruiqi Lian, Jason H. Lin, Lixia Liu, Tao Liu, Roy Ju: Shangri-La: achieving high performance from compiled network applications while enabling ease of programming. PLDI 2005: 224-236 |
2004 | ||
34 | EE | Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai: A Compiler Framework for Recovery Code Generation in General Speculative Optimizations. IEEE PACT 2004: 17-28 |
33 | EE | Chengyong Wu, Ruiqi Lian, Junchao Zhang, Roy Ju, Sun Chan, Lixia Liu, Xiaobing Feng, Zhaoqing Zhang: An Overview of the Open Research Compiler. LCPC 2004: 17-31 |
32 | EE | Gilberto Contreras, Margaret Martonosi, Jinzhan Peng, Roy Ju, Guei-Yuan Lueh: XTREM: a power simulator for the Intel XScale® core. LCTES 2004: 115-125 |
31 | EE | Peng-Sheng Chen, Yuan-Shin Hwang, Roy Dz-Ching Ju, Jenq Kuen Lee: Interprocedural Probabilistic Pointer Analysis. IEEE Trans. Parallel Distrib. Syst. 15(10): 893-907 (2004) |
30 | EE | Dong-yuan Chen, Lixia Liu, Roy Dz-Ching Ju, Chen Fu, Shuxin Yang, Chengyong Wu: Efficient Modeling of Itanium Architecture during Instruction Scheduling using Extended Finite State Automata. J. Instruction-Level Parallelism 6: (2004) |
29 | EE | Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan: A compiler framework for speculative optimizations. TACO 1(3): 247-271 (2004) |
2003 | ||
28 | EE | Liu Yang, Sun Chan, Guang R. Gao, Roy Ju, Guei-Yuan Lueh, Zhaoqing Zhang: Inter-procedural stacked register allocation for itanium® like architecture. ICS 2003: 215-225 |
27 | EE | Dong-yuan Chen, Lixia Liu, Chen Fu, Shuxin Yang, Chengyong Wu, Roy Dz-Ching Ju: Efficient Resource Management during Instruction Scheduling for the EPIC Architecture. IEEE PACT 2003: 36-45 |
26 | EE | Youfeng Wu, Li-Ling Chen, Roy Ju, Jesse Fang: Performance potentials of compiler-directed data speculation. ISPASS 2003: 22-31 |
25 | EE | Yang Liu, Zhaoqing Zhang, Ruliang Qiao, Roy Dz-Ching Ju: A Region-Based Compilation Infrastructure. Interaction between Compilers and Computer Architectures 2003: 75-84 |
24 | EE | Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan: A compiler framework for speculative analysis and optimizations. PLDI 2003: 289-299 |
23 | EE | Peng-Sheng Chen, Ming-Yu Hung, Yuan-Shin Hwang, Roy Dz-Ching Ju, Jenq Kuen Lee: Compiler support for speculative multithreading architecture with probabilistic points-to analysis. PPOPP 2003: 25-36 |
22 | EE | Gwan-Hwan Hwang, Cheng-Wei Chen, Jenq Kuen Lee, Roy Dz-Ching Ju: Segmented Alignment: An Enhanced Model to Align Data Parallel Programs of HPF. The Journal of Supercomputing 25(1): 17-41 (2003) |
2001 | ||
21 | EE | Srikanth T. Srinivasan, Roy Dz-Ching Ju, Alvin R. Lebeck, Chris Wilkerson: Locality vs. criticality. ISCA 2001: 132-143 |
20 | EE | Yuan-Shin Hwang, Peng-Sheng Chen, Jenq Kuen Lee, Roy Dz-Ching Ju: Probabilistic Points-to Analysis. LCPC 2001: 290-305 |
19 | EE | Gwan-Hwan Hwang, Jenq Kuen Lee, Roy Dz-Ching Ju: Array Operation Synthesis to Optimize HPF Programs on Distributed Memory Machines. J. Parallel Distrib. Comput. 61(4): 467-500 (2001) |
2000 | ||
18 | EE | Roy Dz-Ching Ju, Kevin Nomura, Uma Mahadevan, Le-Chun Wu: A Unified Compiler Framework for Control and Data Speculation. IEEE PACT 2000: 157-168 |
17 | EE | Uma Mahadevan, Kevin Nomura, Roy Dz-Ching Ju, Rick Hank: Applying Data Speculation in Modulo Scheduled Loops. IEEE PACT 2000: 169-178 |
16 | Jens Knoop, Jean-Francois Collard, Roy Dz-Ching Ju: Partial Redundancy Elimination on Predicated Code. SAS 2000: 260-279 | |
1999 | ||
15 | EE | Vugranam C. Sreedhar, Roy Dz-Ching Ju, David M. Gillies, Vatsa Santhanam: Translating Out of Static Single Assignment Form. SAS 1999: 194-210 |
1998 | ||
14 | A. V. S. Sastry, Roy Dz-Ching Ju: A New Algorithm for Scalar Register Promotion based on SSA Form. PLDI 1998: 15-25 | |
13 | Gwan-Hwan Hwang, Jenq Kuen Lee, Roy Dz-Ching Ju: A Function-Composition Approach to Synthesize Fortran 90 Array Operations. J. Parallel Distrib. Comput. 54(1): 1-47 (1998) | |
1997 | ||
12 | EE | Ted Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Passos, Roy Dz-Ching Ju: Algorithm and Hardware Support for Branch Anticipation. Great Lakes Symposium on VLSI 1997: 163- |
11 | Gwan-Hwan Hwang, Jenq Kuen Lee, Roy Dz-Ching Ju: Integrating Automatic Data Alignment and Array Operation Synthesis to Optimize Data Parallel Programs. LCPC 1997: 412-415 | |
1996 | ||
10 | Gwan-Hwan Hwang, Jenq Kuen Lee, Roy Dz-Ching Ju: Array Operation Synthesis to Optimize HPF Programs. ICPP, Vol. 3 1996: 1-8 | |
9 | EE | David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker: Global Predicate Analysis and Its Application to Register Allocation. MICRO 1996: 114-125 |
1995 | ||
8 | Gwan-Hwan Hwang, Jenq Kuen Lee, Roy Dz-Ching Ju: An Array Operation Synthesis Scheme to Optimize Fortran 90 Programs. PPOPP 1995: 112-122 | |
1994 | ||
7 | Dz-Ching Ju, Chuan-lin Wu, Paul R. Carini: Statement Merge: an Inter-Statement Optimization of Array Language Programs. ICPP 1994: 126-129 | |
6 | EE | Dz-Ching Ju, Chuan-lin Wu, Paul R. Carini: The Classification, Fusion, and Parallelization of Array Language Primitives. IEEE Trans. Parallel Distrib. Syst. 5(10): 1113-1120 (1994) |
1993 | ||
5 | Wai-Mee Ching, Paul R. Carini, Dz-Ching Ju: A Primitive-Based Strategy for Producing Efficient Code for Very High Level Programs. Comput. Lang. 19(1): 41-50 (1993) | |
1992 | ||
4 | Dz-Ching Ju, Chuan-lin Wu, Paul R. Carini: The Synthesis of Array Functions and Its Use in Parallel Computation. ICPP (2) 1992: 293-296 | |
1991 | ||
3 | EE | Dz-Ching Ju, Wai-Mee Ching, Chuan-lin Wu: On Performance and Space Usage Improvements for Parallelized Compiled APL Code. APL 1991: 234-243 |
2 | Dz-Ching Ju, Wai-Mee Ching: Exploitation of APL Data Parallelism on a Shared-memory MIMD Machine. PPOPP 1991: 61-72 | |
1 | Wai-Mee Ching, Dz-Ching Ju: Execution of automatically parallelized APL programs on RP3. IBM Journal of Research and Development 35(5): 767-778 (1991) |