12. IPPS / 9. SPDP 1998:
Orlando,
Florida,
USA
12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30 - April 3, 1998, Orlando, Florida, USA, Proceedings.
IEEE Computer Society 1998, ISBN 0-8186-8403-8 BibTeX
@proceedings{DBLP:conf/ipps/1998,
title = {12th International Parallel Processing Symposium / 9th Symposium
on Parallel and Distributed Processing (IPPS/SPDP '98), March
30 - April 3, 1998, Orlando, Florida, USA, Proceedings},
booktitle = {IPPS/SPDP},
publisher = {IEEE Computer Society},
year = {1998},
isbn = {0-8186-8403-8},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Communication
Session 2:
Compilers I
- Bo Lu, John M. Mellor-Crummey:
Compiler-Optimization of Implicit Reductions for Distributed Memory Multiprocessors.
42-51
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- Gerardo Bandera, Pablo P. Trabado, Emilio L. Zapata:
Local Enumeration Techniques for Sparse Algorithms.
52-56
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- Yi Tian, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, Peter M. Kogge:
Optimizing Data Scheduling on Processor-in-Memory Arrays.
57-61
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- Gwan-Hwan Hwang, Jenq Kuen Lee:
An Expression-Rewriting Framework to Generic Communication Sets for HPF Programs with Block-Cyclic Distribution.
62-68
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- Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, U. Nagaraj Shenoy:
A Generalized Framework for Global Communication Optimization.
69-73
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- Dhruva R. Chakrabarti, Prithviraj Banerjee, Antonio Lain:
Evaluation of Compiler and Runtime Library Approaches for Supporting Parallel Regular Applications.
74-79
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Session 3:
Mathematical Applications
- Michael J. Quinn, Alexey G. Malishevsky, Nagajagadeswar Seelam, Yan Zhao:
Preliminary Results from a Parallel MATLAB Compiler.
81-87
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- Dolors Royo, Antonio González, Miguel Valero-García:
Jacobi Orderings for Multi-Port Hypercubes.
88-97
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- Paul D. Hovland, Christian H. Bischof:
Automatic Differentiation for Message-Passing Parallel Programs.
98-104
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- Peter R. Cappello, Ömer Egecioglu:
Processor Lower Bound Formulas for Array Computations and Parametric Diophantine Systems.
105-109
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- John A. Gunnels, Calvin Lin, Greg Morrow, Robert A. van de Geijn:
A Flexible Class of Parallel Matrix Multiplication Algorithms.
110-116
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- Peter Sulatycke, Kanad Ghose:
Caching-Efficient Multithreaded Fast Multiplication of Sparse Matrices.
117-123
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Session 4:
Networks
- Yuanyuan Yang, Jianchao Wang, Yi Pan:
Permutation Capability of Optical Multistage Interconnect Networks.
125-133
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- Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. Panda:
HIPIQS: A High-Performance Switch Architecture Using Input Queuing.
134-143
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- Claudson F. Bornstein, Ami Litman, Bruce M. Maggs, Ramesh K. Sitaraman, Tal Yatzkar:
On the Bisection Width and Expansion of Butterfly Networks.
144-150
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- David Coudert, Afonso Ferreira, Xavier Muñoz:
Multiprocessor Architectures Using Multi-Hop Multi-OPS Lightwave Networks and Distributed Control.
151-155
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- Charles A. Salisbury, Rami G. Melhem:
Distributed Dynamic Control of Circuit-Switched Banyan Networks.
156-161
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- Raymond Hoare, Henry G. Dietz:
A Case for Aggregate Networks.
162-166
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Session 5:
Compilers II
- Ramaswamy Govindarajan, N. S. S. Narasimha Rao, Erik R. Altman, Guang R. Gao:
An Enhanced Co-Scheduling Method Using Reduced MS-State Diagrams.
168-175
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- Dragan Milicev, Zoran Jovanovic:
Predicated Software Pipelining Technique for Loops with Conditions.
176-180
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- Weng-Long Chang, Chih-Ping Chu, Jesse Wu:
The Generalized Lambda Test.
181-186
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- Yunheung Paek, David A. Padua:
Experimental Study of Compiler Techniques for NUMA Machines.
187-193
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- Amod K. Dani, V. Janaki Ramanan, Ramaswamy Govindarajan:
Register-Sensitive Software Pipelining.
194-198
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- M. Srinivas, Alexandru Nicolau:
Analyzing the Individual/Combined Effects of Speculative and Guarded Execution on a Superscalar Architecture.
199-208
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Session 6:
Signal and Image Processing
- Frank Munz, T. Stephan, Ursula Maier, Thomas Ludwig, Arndt Bode, Sibylle Ziegler, Stephan G. Nekolla, P. Bartenstein, Markus Schwaiger:
NOW Parallel Reconstruction of Functional Images.
210-214
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- Neelima Gupta, Sandeep Sen:
An Improved Output-Size Sensitive Parallel Algorithm for Hidden-Surface Removal for Terrains.
215-219
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- Alok N. Choudhary, Wei-keng Liao, Donald Weiner, Pramod K. Varshney, Richard W. Linderman, Mark H. Linderman:
Design, Implementation and Evaluation of Parallel Pipelined STAP on Parallel Computers.
220-225
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- Mikael Taveniku, Anders Ahlander, Magnus Jonsson, Bertil Svensson:
The VEGA Moderately Parallel MIMD, Moderately Parallel SIMD, Architectures for High Performance Array Signal Processing.
226-232
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- Christoph Giess, Achim Mayer, Harald Evers, Hans-Peter Meinzer:
Medical Image Processing and Visualization on Heterogeneous Clusters of Symmetric Multiprocessors Using MPI and POSIX Threads.
233-237
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- R. Sernec, M. Zajc, Jurij F. Tasic:
A Quantitative Code Analysis of Scientific Systolic Programs: DSP vs. Matrix Algorithms.
238-242
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Session 7:
Collective Communication
- Ran Libeskind-Hadas, Dominic Mazzoni, Ranjith Rajagopalan:
Tree-Based Multicasting in Wormhole-Routed Irregular Topologies.
244-249
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- Thomas Hopfner, Franz Fischer, Georg Färber:
NoWait-RPC: Extending ONC RPC to a Fully Compatible Message Passing System.
250-254
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- Jin-Soo Kim, Soonhoi Ha, Chu Shik Jhon:
Efficient Barrier Synchronization Mechanism for BSP Model on Message Passing Architectures.
255-259
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- Gautam Shah, Jarek Nieplocha, Jamshed H. Mirza, Chulho Kim, Robert J. Harrison, Rama Govindaraju, Kevin J. Gildea, Paul DiNicola, Carl A. Bender:
Performance and Experience with LAPI - a New High-Performance Communication Library for the IBM RS/6000 SP.
260-266
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- Fabrizio Petrini:
Total Exchange on k-ary n-cubes with Adaptive Routing.
267-271
Electronic Edition (link) BibTeX
- Steven Lumetta, David E. Culler:
Managing Concurrent Access for Shared Memory Active Messages.
272-278
Electronic Edition (link) BibTeX
Session 8:
Memory Hierarchy and I/O
- Jaechun No, Sung-Soon Park, Jesús Carretero, Alok N. Choudhary, Pang Chen:
Design and Implementation of a Parallel I/O Runtime System for Irregular Applications.
280-284
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- Ian Parsons, Jonathan Schaeffer, Duane Szafron, Ronald C. Unrau:
Using PI/OT to Support Complex Parallel I/O.
285-291
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- Chidamber Kulkarni, Francky Catthoor, Hugo De Man:
Code Transformations for Low Power Caching in Embedded Multimedia Processors.
292-297
Electronic Edition (link) BibTeX
- Ibraheem Al-Furaih, Sanjay Ranka:
Memory Hierarchy Management for Iterative Graph Structures.
298-302
Electronic Edition (link) BibTeX
- Jang Sun Lee, Sung Hoon Ko, Sanjay Ranka, Byung Eui Min:
High-Performance External Computations Using User-Controllable I/O.
303-307
Electronic Edition (link) BibTeX
- Hiroshi Tezuka, Francis O'Carroll, Atsushi Hori, Yutaka Ishikawa:
Pin-Down Cache: A Virtual Memory Management Technique for Zero-Copy Communication.
308-314
Electronic Edition (link) BibTeX
Session 9:
Algorithms I
- Graham M. Megson, I. M. Bland:
Synthesis of a Systolic Array Genetic Algorithm.
316-320
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- Seungjo Bae, Dongmin Kim, Sanjay Ranka:
Vector Prefix and Reduction Computation on Coarse-Grained, Distributed-Memory Parallel Machines.
321-325
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- Yuji Shinano, Tetsuya Fujie, Yoshiko Ikebe, Ryuichi Hirabayashi:
Solving the Maximum Clique Problem Using PUBB.
326-332
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- Rong Lin, Koji Nakano, Stephan Olariu, Maria Cristina Pinotti, James L. Schwing, Albert Y. Zomaya:
A Scalable VLSI Architecture for Binary Prefix Sums.
333-337
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- Bojana Obrenic:
Emulating Direct Products by Index-Shuffle Graphs.
338-344
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- Lee Wang, Anthony A. Maciejewski, Howard Jay Siegel, Vwani P. Roychowdhury:
A Comparative Study of Five Parallel Genetic Algorithms Using the Traveling Salesman Problem.
345-349
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Session 10:
Routing
Session 11:
Operating Systems and Scheduling
- Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham:
Partitioned Schedules for Clustered VLIW Architectures.
386-391
Electronic Edition (link) BibTeX
- Kelvin K. Yue, David J. Lilja:
Dynamic Processor Allocation with the Solaris Operating System.
392-397
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- Shivakant Mishra, Rongguang Yang:
Thread-Based vs Event-Based Implementation of a Group Communication Service.
398-402
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- Sivarama P. Dandamudi, Hai Yu:
Performance Sensitivity of Space Sharing Processor Scheduling in Distributed-Memory Multicomputers.
403-409
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- Boris Weissman, Benedict Gomes, Jürgen Quittek, Michael Holtkamp:
Efficient Fine-Grain Thread Migration with Active Threads.
410-414
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- Miquel A. Senar, Ana Ripoll, Ana Cortés, Emilio Luque:
Clustering and Reassignment-Based Mapping Strategy for Message Passing Architectures.
415-421
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Session 12:
Algorithms II
Session 13:
Multiprocessor Performance Evaluation
- Laxmi N. Bhuyan, Hu-Jun Wang, Ravi R. Iyer, Akhilesh Kumar:
Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors.
466-474
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- Hongzhang Shan, Jaswinder Pal Singh:
Parallel Tree Building on a Range of Shared Address Space Multiprocessors: Algorithms and Application Performance.
475-484
Electronic Edition (link) BibTeX
- Gheith A. Abandah, Edward S. Davidson:
Configuration Independent Analysis for Characterizing Shared-Memory Applications.
485-491
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- Ben H. H. Juurlink:
Experimental Validation of Parallel Computation Models on the Intel Paragon.
492-497
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- Lars Lundberg, Håkan Lennerstad:
Comparing the Optimal Performance of Different MIMD Multiprocessor Architectures.
498-502
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- Ashwini K. Nanda, Yiming Hu, Moriyoshi Ohara, Caroline Benveniste, Mark Giampapa, Maged M. Michael:
The Design of COMPASS: An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors.
503-509
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Session 14:
Scheduling
Session 15:
Databases and Sorting
Industrial Track:
Session I Environments,
Tools,
and Evaluation Methods
Industrial Track:
Session II Reconfigurable Systems
Session 16:
Performance Prediction and Evaluation
Session 17:
Software Distributed Shared Memory
Session 18:
Scientific Simulation
Session 19:
Fault Tolerance
Session 20:
Performance and Debugging Tools
Session 21:
Distributed Systems
Copyright © Sat May 16 23:24:26 2009
by Michael Ley (ley@uni-trier.de)
