CASES 2004: Washington, DC, USA

Mary Jane Irwin, Wei Zhao, Luciano Lavagno, Scott A. Mahlke (Eds.): Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004. ACM 2004, ISBN 1-58113-890-3 BibTeX

Kees A. Vissers:
Programming models and architectures for FPGA platforms. 1
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Memory systems

Ali El-Haj-Mahmoud, Eric Rotenberg:
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. 2-13
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Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy:
Dynamic on-chip memory management for chip multiprocessors. 14-23
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Ken W. Batcher, Robert A. Walker:
Cluster miss prediction with prefetch on miss for embedded CPU instruction caches. 24-34
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Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T. Kandemir:
Reducing energy consumption of queries in memory-resident database systems. 35-45
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Application specific processors

Binu K. Mathew, Al Davis, Michael Parker:
A low power architecture for embedded perception. 46-56
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Timothy Sherwood, Mark Oskin, Brad Calder:
Balancing design options with Sherpa. 57-68
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Pan Yu, Tulika Mitra:
Scalable custom instructions identification for instruction-set extensible processors. 69-78
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Jesus Garcia, Mark G. Arnold, Leonidas L. Bleris, Mayuresh V. Kothare:
LNS architectures for embedded model predictive control processors. 79-84
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Low power SOCs and NOCs

Giovanni Beltrame, Gianluca Palermo, Donatella Sciuto, Cristina Silvano:
Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs. 85-92
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Ravishankar Rao, Sarma B. K. Vrudhula, Musaravakkam S. Krishnan:
Disk drive energy optimization for audio-video applications. 93-103
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Noel Eisley, Li-Shiuan Peh:
High-level power analysis for on-chip networks. 104-115
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Shaoxiong Hua, Gang Qu:
Energy-efficient dual-voltage soft real-time system with (m, k)-firm deadline guarantee. 116-123
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Low power processors

Bramha Allu, Wei Zhang:
Static next sub-bank prediction for drowsy instruction cache. 124-131
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Montserrat Ros, Peter Sutton:
A hamming distance based VLIW/EPIC code compression technique. 132-139
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Linwei Niu, Gang Quan:
Reducing both dynamic and leakage energy consumption for hard real-time systems. 140-148
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Wei Zhang, Bramha Allu:
Loop-based leakage control for branch predictors. 149-155
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John Cornish:
Balanced energy optimization. 156
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Compiler analysis and optimization

Ramakrishnan Venkitaraman, Gopal Gupta:
Static program analysis of embedded executable assembly code. 157-166
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Vasanth Asokan, Alexander G. Dean:
Providing time- and space- efficient procedure calls for asynchronous software thread integration. 167-178
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Klaus Schneider, Jens Brandt, Tobias Schüle:
Causality analysis of synchronous programs with delayed actions. 179-189
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Meilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha:
General loop fusion technique for nested loops considering timing and code size. 190-201
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Co-design and synthesis

David Berner, Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla:
Modular design through component abstraction. 202-211
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Valentina Salapura, Christos J. Georgiou, Indira Nair:
An efficient system-on-a-chip design methodology for networking applications. 212-219
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Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
Translating affine nested-loop programs to process networks. 220-229
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Mary Kiemb, Kiyoung Choi:
Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems. 230-237
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Memory optimization

Steve Carr, Philip H. Sweany:
Automatic data partitioning for the agere payload plus network processor. 238-247
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Sven Verdoolaege, Rachid Seghir, Kristof Beyls, Vincent Loechner, Maurice Bruynooghe:
Analytical computation of Ehrhart polynomials: enabling more compiler analyses and optimizations. 248-258
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Federico Angiolini, Francesco Menichelli, Alberto Ferrero, Luca Benini, Mauro Olivieri:
A post-compiler approach to scratchpad mapping of code. 259-267
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Christophe Guillon, Fabrice Rastello, Thierry Bidault, Florent Bouchez:
Procedure placement using temporal-ordering information: dealing with code size expansion. 268-279
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Reliability and security

Surupa Biswas, Matthew Simpson, Rajeev Barua:
Memory overflow protection for embedded systems using run-time checks, reuse and compression. 280-291
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Xiaotong Zhuang, Tao Zhang, Hsien-Hsin S. Lee, Santosh Pande:
Hardware assisted control flow obfuscation for embedded processors. 292-302
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Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede:
Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques. 303-311
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