| 2008 |
|---|
| 5 | EE | Hiroaki Shikano,
Masaki Ito,
Kunio Uchiyama,
Toshihiko Odaka,
Akihiro Hayashi,
Takeshi Masuura,
Masayoshi Mase,
Jun Shirako,
Yasutaka Wada,
Keiji Kimura,
Hironori Kasahara:
Software-cooperative power-efficient heterogeneous multi-core for media processing.
ASP-DAC 2008: 736-741 |
| 4 | EE | Hiroaki Shikano,
Jun Shirako,
Yasutaka Wada,
Keiji Kimura,
Hironori Kasahara:
Power-Aware Compiler Controllable Chip Multiprocessor.
IEICE Transactions 91-C(4): 432-439 (2008) |
| 3 | EE | Tadayoshi Enomoto,
Suguru Nagayama,
Hiroaki Shikano,
Yousuke Hagiwara:
Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array.
IEICE Transactions 91-C(4): 553-561 (2008) |
| 2007 |
|---|
| 2 | EE | Hiroaki Shikano,
Jun Shirako,
Yasutaka Wada,
Keiji Kimura,
Hironori Kasahara:
Power-Aware Compiler Controllable Chip Multiprocessor.
PACT 2007: 427 |
| 2005 |
|---|
| 1 | EE | Jun Shirako,
Naoto Oshiyama,
Yasutaka Wada,
Hiroaki Shikano,
Keiji Kimura,
Hironori Kasahara:
Compiler Control Power Saving Scheme for Multi Core Processors.
LCPC 2005: 362-376 |
