| 2007 |
|---|
| 10 | EE | Pierre Michaud,
André Seznec,
Damien Fetis,
Yiannakis Sazeides,
Theofanis Constantinou:
A study of thread migration in temperature-constrained multicores.
TACO 4(2): (2007) |
| 2005 |
|---|
| 9 | EE | Theofanis Constantinou,
Yiannakis Sazeides,
Pierre Michaud,
Damien Fetis,
André Seznec:
Performance implications of single thread migration on a chip multi-core.
SIGARCH Computer Architecture News 33(4): 80-91 (2005) |
| 2004 |
|---|
| 8 | EE | Pierre Michaud:
Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration.
HPCA 2004: 186-197 |
| 2003 |
|---|
| 7 | EE | Pierre Michaud:
A statistical model of skewed-associativity.
ISPASS 2003: 204-213 |
| 2002 |
|---|
| 6 | EE | Pierre Michaud,
Christian Saguez:
A Learning Grid for the multichallenge school ECP.
LeGE-WG 1 2002 |
| 2001 |
|---|
| 5 | EE | Pierre Michaud,
André Seznec:
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors.
HPCA 2001: 27-36 |
| 4 | | Pierre Michaud,
André Seznec,
Stéphan Jourdan:
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors.
International Journal of Parallel Programming 29(1): 35-58 (2001) |
| 1999 |
|---|
| 3 | EE | Pierre Michaud,
André Seznec,
Stéphan Jourdan:
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.
IEEE PACT 1999: 2-10 |
| 1997 |
|---|
| 2 | EE | Pierre Michaud,
André Seznec,
Richard Uhlig:
Trading Conflict and Capacity Aliasing in Conditional Branch Predictors.
ISCA 1997: 292-303 |
| 1996 |
|---|
| 1 | | André Seznec,
Stéphan Jourdan,
Pascal Sainrat,
Pierre Michaud:
Multiple-Block Ahead Branch Predictors.
ASPLOS 1996: 116-127 |
