2008 |
24 | EE | Hao Li,
Jian Huang,
Philip H. Sweany,
Dijiang Huang:
FPGA implementations of elliptic curve cryptography and Tate pairing over a binary field.
Journal of Systems Architecture - Embedded Systems Design 54(12): 1077-1088 (2008) |
2007 |
23 | | Jian Huang,
Hao Li,
Philip H. Sweany:
An FPGA implementation of elliptic curve cryptography for future secure web transaction.
ISCA PDCS 2007: 296-301 |
22 | EE | Wentong Li,
Mehran Rezaei,
Krishna M. Kavi,
Afrin Naz,
Philip H. Sweany:
Feasibility of decoupling memory management from the execution pipeline.
Journal of Systems Architecture 53(12): 927-936 (2007) |
2006 |
21 | | Wentong Li,
Krishna M. Kavi,
Afrin Naz,
Philip H. Sweany:
Speculative Thread Execution in a Multithreaded Dataflow Architecture.
ISCA PDCS 2006: 102-107 |
20 | | Afrin Naz,
Krishna M. Kavi,
Philip H. Sweany,
Wentong Li:
A Study of Reconfigurable Split Data Caches and Instruction Caches.
ISCA PDCS 2006: 235-240 |
19 | EE | Afrin Naz,
Krishna M. Kavi,
Wentong Li,
Philip H. Sweany:
Tiny split data-caches make big performance impact for embedded applications.
J. Embedded Computing 2(2): 207-219 (2006) |
2005 |
18 | EE | Afrin Naz,
Mehran Rezaei,
Krishna M. Kavi,
Philip H. Sweany:
Improving data cache performance with integrated use of split caches, victim cache and stream buffers.
SIGARCH Computer Architecture News 33(3): 41-48 (2005) |
2004 |
17 | EE | Steve Carr,
Philip H. Sweany:
Automatic data partitioning for the agere payload plus network processor.
CASES 2004: 238-247 |
16 | | Afrin Naz,
Krishna M. Kavi,
Philip H. Sweany,
Mehran Rezaei:
A Study of Separate Array and Scalar Caches.
HPCS 2004: 157-164 |
2003 |
15 | EE | Steve Carr,
Philip H. Sweany:
An experimental evaluation of scalar replacement on scientific benchmarks.
Softw., Pract. Exper. 33(15): 1419-1445 (2003) |
2002 |
14 | EE | Yi Qian,
Steve Carr,
Philip H. Sweany:
Optimizing Loop Performance for Clustered VLIW Architectures.
IEEE PACT 2002: 271-280 |
13 | EE | Yi Qian,
Steve Carr,
Philip H. Sweany:
Loop fusion for clustered VLIW architectures.
LCTES-SCOPES 2002: 112-119 |
2001 |
12 | | Xianglong Huang,
Steve Carr,
Philip H. Sweany:
Loop Transformations for Architectures with Partitioned Register Banks.
LCTES/OM 2001: 48-55 |
2000 |
11 | EE | Jason Hiser,
Steve Carr,
Philip H. Sweany:
Global Register Partitioning.
IEEE PACT 2000: 13-23 |
10 | EE | Jason Hiser,
Steve Carr,
Philip H. Sweany,
Steven J. Beaty:
Register Assignment for Software Pipelining with Partitioned Register Banks.
IPDPS 2000: 211-218 |
1998 |
9 | EE | Philip H. Sweany,
Steve Carr,
Brett L. Huber:
Compiler Optimization for Superscalar Systems: Global Instruction Scheduling without Copies.
Digital Technical Journal 10(1): (1998) |
8 | | Vicki H. Allan,
Steven J. Beaty,
Bogong Su,
Philip H. Sweany:
Building a Retargetable Local Instruction Scheduler.
Softw., Pract. Exper. 28(3): 249-283 (1998) |
1997 |
7 | | Chen Ding,
Steve Carr,
Philip H. Sweany:
Modulo Scheduling with Cache Reuse Information.
Euro-Par 1997: 1079-1083 |
1996 |
6 | EE | Steve Carr,
Chen Ding,
Philip H. Sweany:
Improving Software Pipelining with Unroll-and-Jam.
HICSS (1) 1996: 183-192 |
5 | EE | Michael J. Bourke III,
Philip H. Sweany,
Steven J. Beaty:
Extending List Scheduling to Consider Execution Frequency.
HICSS (1) 1996: 193-202 |
1992 |
4 | EE | Philip H. Sweany,
Steven J. Beaty:
Dominator-path scheduling: a global scheduling method.
MICRO 1992: 260-263 |
1990 |
3 | EE | Philip H. Sweany,
Steven J. Beaty:
Post-compaction register assignment in a retargetable compiler.
MICRO 1990: 107-116 |
1988 |
2 | EE | Robert A. Mueller,
Michael R. Duda,
Philip H. Sweany,
Jack S. Walicki:
Horizon: A Retargetable Compiler for Horizontal Microarchitectures.
IEEE Trans. Software Eng. 14(5): 575-583 (1988) |
1987 |
1 | EE | Michael A. Howland,
Robert A. Mueller,
Philip H. Sweany:
Trace scheduling optimization in a retargetable microcode compiler.
MICRO 1987: 106-114 |