| 2008 |
|---|
| 8 | EE | John D. Davis,
Zhangxi Tan,
Fang Yu,
Lintao Zhang:
A practical reconfigurable hardware accelerator for Boolean satisfiability solvers.
DAC 2008: 780-785 |
| 7 | EE | Martha Mercaldi Kim,
John D. Davis,
Mark Oskin,
Todd M. Austin:
Polymorphic On-Chip Networks.
ISCA 2008: 101-112 |
| 6 | EE | John D. Davis,
Zhangxi Tan,
Fang Yu,
Lintao Zhang:
Designing an Efficient Hardware Implication Accelerator for SAT Solving.
SAT 2008: 48-62 |
| 5 | EE | Nitin Agrawal,
Vijayan Prabhakaran,
Ted Wobber,
John D. Davis,
Mark S. Manasse,
Rina Panigrahy:
Design Tradeoffs for SSD Performance.
USENIX Annual Technical Conference 2008: 57-70 |
| 2005 |
|---|
| 4 | EE | John D. Davis,
James Laudon,
Kunle Olukotun:
Maximizing CMP Throughput with Mediocre Cores.
IEEE PACT 2005: 51-62 |
| 3 | EE | John D. Davis,
Cong Fu,
James Laudon:
The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors.
SIGARCH Computer Architecture News 33(4): 14-23 (2005) |
| 2 | EE | John D. Davis,
Stephen E. Richardson,
Charis Charitsis,
Kunle Olukotun:
A chip prototyping substrate: the flexible architecture for simulation and testing (FAST).
SIGARCH Computer Architecture News 33(4): 34-43 (2005) |
| 2004 |
|---|
| 1 | EE | Lance Hammond,
Vicky Wong,
Michael K. Chen,
Brian D. Carlstrom,
John D. Davis,
Ben Hertzberg,
Manohar K. Prabhu,
Honggo Wijaya,
Christos Kozyrakis,
Kunle Olukotun:
Transactional Memory Coherence and Consistency.
ISCA 2004: 102-113 |
