29. ISMVL 1999: Freiburg im Breisgau, Germany

29th IEEE International Symposium on Multiple-Valued Logic (ISMVL 1999), 20-22 May, 1999, Freiburg im Breisgau, Germany, Proceedings. IEEE Computer Society, 1999

Invited Address

Toshio Baba:
Development of Quantum Functional Devices for Multiple-Valued Logic Circuits. 2-8
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Algebra I

Michel Serfati:
Multivalued Binary Relations and Post Algebras. 10-17
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Radomir S. Stankovic, Dejan Milenovic, Dragan Jankovic:
Quaternion Groups versus Dyadic Groups in Representations and Processing of Switching Functions. 18-23
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Szymon Jaroszewicz, Dan A. Simovici:
On Axiomatization of Conditional Entropy of Functions Between Finite Sets. 24-28
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Circuits I

Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama:
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. 30-35
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Claudio Moraga, Ralph Heider:
"New lamps for old!" (Generalized Multiple-valued Neurons). 36-41
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Edgar "Dan" Olson:
Supplementary Symmetrical Logic Circuit Structure. 42-47
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Decomposition

Bernd Steinbach, Marek A. Perkowski, Christian Lang:
Bi-Decompositions of Multi-Valued Functions for Circuit Design and Data Mining Applications. 50-58
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Tsutomu Sasao:
Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions. 59-65
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J. J. Lou, Janusz A. Brzozowski:
A Generalization of Shestakov's Function Decomposition Method. 66-71
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Clones

Ivo G. Rosenberg, Hajime Machida:
Gigantic Pairs of Minimal Clones. 74-79
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Lucien Haddad, Jean Fugère:
Maximal Chains of Partial Clones Containing All Idempotent Partial Functions. 80-84
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Lucien Haddad, Dietlinde Lau:
Partial Clones and their Generating Sets. 85-90
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Logic Design

Elena Dubrova:
Evaluation of m-Valued Fixed Polarity Generalizations of Reed-Muller Canonical Form. 92-98
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Debatosh Debnath, Tsutomu Sasao:
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates. 99-104
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Takahiro Hozumi, Osamu Kakusho, Yutaka Hata:
The Output Permutation for the Multiple-Valued Logic Minimization with Universal Literals. 105-109
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Noboru Takagi, Akimitsu Hon-nami, Kyoichi Nakashima:
Logical Model for Representing Uncertain Statuses of Multiple-Valued Logic Systems Realized by Min, Max and Literals. 110-115
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Algebra II

Gerhard W. Dueck, Mou Hu, Blair Fraser:
A Super Switch Algebra for Quantum Device Based Systems. 118-124
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Tomoko Ninomiya, Masao Mukaidono:
Clarifying the Axioms of Kleene Algebra based on the Method of Indeterminate Coefficients. 125-130
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Grant Pogosyan:
The Number of Cascade Functions. 131-135
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Renren Liu:
Research on the Similarity among Precomplete Sets Preserving m-ary Relations in Partial K-Valued Logic. 136-139
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Invited Address

Abdelwaheb Ayari, David A. Basin, Stefan Friedrich:
Structural and Behavioral Modeling with Monadic Logics. 142-151
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Decision Diagrams

Radomir S. Stankovic:
Matrix-Valued EXOR-TDDs in Decompositon of Switching Functions. 154-159
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Mostafa H. Abd-El-Barr, Henry Fernandes:
Synthesis of Multiple-Valued Decision Diagrams using Current-Mode CMOS Circuits. 160-165
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Hafiz Md. Hasan Babu, Tsutomu Sasao:
Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions. 166-172
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Circuits II

Andreas Herrfeld, Siegbert Hentschke:
Ternary Multiplication Circuits Using 4-Input Adder Cells and Carry Look-Ahead. 174-179
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Jing Shen, Koichi Tanno, Okihiko Ishizuka:
Down Literal Circuit with Neuron-MOS Transistors and Its Applications. 180-185
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Aryan Saed, Majid Ahmadi, Graham A. Jullien:
Arithmetic Circuits for Analog Digits. 186-191
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Applications

Kai Freitag, Lars Hildebrand, Claudio Moraga:
Quaternary Coded Genetic Algorithms. 194-199
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Takafumi Aoki, Ken-ichi Hoshi, Tatsuo Higuchi:
Redundant Complex Arithmetic and Its Application to Complex Multiplier Design. 200-207
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Alioune Ngom, Ivan Stojmenovic, Jovisa D. Zunic:
On the Number of Multilinear Partitions and the Computing Capacity of Multiple-Valued Multiple-Threshold Perceptrons. 208-213
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Yasunori Nagata, D. Michael Miller, Masao Mukaidono:
B-ternary Logic Based Asynchronous Micropipeline. 214-219
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K. J. Adams, J. G. Campbell, Liam P. Maguire, J. A. C. Webb:
State Assignment Techniques in Multiple-Valued Logic. 220-225
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Logic

Lech Józwiak:
Information Relationships and Measures in Application to Logic Design. 228-235
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Thomas Lukasiewicz:
Probabilistic and Truth-Functional Many-Valued Logic Programming. 236-241
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Viorica Sofronie-Stokkermans:
Representation Theorems and Theorem Proving in Non-Classical Logics. 242-247
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Bernhard Beckert, Reiner Hähnle, Felip Manyà:
Transformations between Signed and Classical Clause Logic. 248-255
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Masahiro Miyakawa:
Semirigid Problems in k-Valued Logic. 256-260
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Testing

Mostafa H. Abd-El-Barr, Maher Al-Sherif, Mohamed Osman:
Fault Characterization and Testability Considerations in Multi-Valued Logic Circuits. 262-267
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Ugur Kalay, Marek A. Perkowski, Douglas V. Hall:
Highly Testable Boolean Ring Logic Circuits. 268-274
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Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama:
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. 275-279
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Fuzzy Logic

Helmut Thiele:
On the Concept of Qualitative Fuzzy Set. 282-287
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Yutaka Hata, Masao Mukaidono:
On Some Classes of Fuzzy Information Granularity and Their Representations. 288-293
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Liam P. Maguire, T. Martin McGinnity, L. J. McDaid:
From a Fuzzy Flip-Flop to a MVL Flip-Flop. 294-299
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