| 2006 |
|---|
| 7 | EE | André DeHon,
Randy Huang,
John Wawrzynek:
Stochastic spatial routing for reconfigurable networks.
Microprocessors and Microsystems 30(6): 301-318 (2006) |
| 6 | EE | André DeHon,
Yury Markovskiy,
Eylon Caspi,
Michael Chu,
Randy Huang,
Stylianos Perissakis,
Laura Pozzi,
Joseph Yeh,
John Wawrzynek:
Stream computations organized for reconfigurable execution.
Microprocessors and Microsystems 30(6): 334-354 (2006) |
| 2003 |
|---|
| 5 | EE | Randy Huang,
John Wawrzynek,
André DeHon:
Stochastic, spatial routing for hypergraphs, trees, and meshes.
FPGA 2003: 78-87 |
| 2002 |
|---|
| 4 | EE | André DeHon,
Randy Huang,
John Wawrzynek:
Hardware-Assisted Fast Routing.
FCCM 2002: 205- |
| 3 | EE | Yury Markovskiy,
Eylon Caspi,
Randy Huang,
Joseph Yeh,
Michael Chu,
John Wawrzynek,
André DeHon:
Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine.
FPGA 2002: 196-205 |
| 2000 |
|---|
| 2 | EE | Eylon Caspi,
Michael Chu,
Randy Huang,
Joseph Yeh,
John Wawrzynek,
André DeHon:
Stream Computations Organized for Reconfigurable Execution (SCORE).
FPL 2000: 605-614 |
| 1999 |
|---|
| 1 | EE | William Tsu,
Kip Macy,
Atul Joshi,
Randy Huang,
Norman Walker,
Tony Tung,
Omid Rowhani,
George Varghese,
John Wawrzynek,
André DeHon:
HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array.
FPGA 1999: 125-134 |
