| |
| 2005 | ||
|---|---|---|
| 4 | EE | Tomoya Kitai, Tomohiro Yoneda, Chris J. Myers: Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation. IEICE Transactions 88-D(11): 2555-2564 (2005) |
| 2002 | ||
| 3 | EE | Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers: Automatic Derivation of Timing Constraints by Failure Analysis. CAV 2002: 195-208 |
| 2 | EE | Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers: Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC 2002: 210-220 |
| 2001 | ||
| 1 | EE | Tomoya Kitai, Tomohiro Yoneda: Partial Order Reduction in Verification of Wheel Structured Parameterized Circuits. PRDC 2001: 173-182 |
| 1 | Eric Mercer (Eric G. Mercer) | [2] |
| 2 | Chris J. Myers | [2] [3] [4] |
| 3 | Yusuke Oguro | [2] |
| 4 | Tomohiro Yoneda | [1] [2] [3] [4] |