ASYNC 1995:
London,
UK
Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK.
IEEE Computer Society 1995 BibTeX
@proceedings{DBLP:conf/async/1995,
title = { Second Working Conference on Asynchronous Design Methodologies,
May 30-31, 1995, London, England, UK},
booktitle = {ASYNC},
publisher = {IEEE Computer Society},
year = {1995},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Pipelines
- David A. Kearney, Neil W. Bergmann:
Performance evaluation of asynchronous logic pipelines with data dependent processing delays.
4-13
Electronic Edition (link) BibTeX
- Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barrios, Raúl Jiménez, José L. Huertas:
New CMOS VLSI linear self-timed architectures.
14-23
Electronic Edition (link) BibTeX
- Jelio T. Yantchev, C. G. Huang, Mark B. Josephs, I. M. Nedelchev:
Low-latency asynchronous FIFO buffers.
24-31
Electronic Edition (link) BibTeX
- Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov:
Designing an asynchronous pipeline token ring interface.
32-
Electronic Edition (link) BibTeX
Silicon Compilation I
Silicon Compilation II
Synthesis/Verification
Testing; Completion-Detection
Microprocessors
- Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt:
ECSTAC: a fast asynchronous microprocessor.
180-189
Electronic Edition (link) BibTeX
- D. K. Arvind, Robert D. Mullins, Vinod E. F. Rebello:
Micronets: a model for decentralising control in asynchronous processor architectures.
190-199
Electronic Edition (link) BibTeX
- C. J. Elston, D. B. Christianson, P. A. Findlay, G. B. Steven:
Hades-towards the design of an asynchronous superscalar processor.
200-209
Electronic Edition (link) BibTeX
- Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu:
ARAS: asynchronous RISC architecture simulator.
210-
Electronic Edition (link) BibTeX
Copyright © Sat May 16 22:58:55 2009
by Michael Ley (ley@uni-trier.de)