7. ASYNC 2001: Salt Lake City, UT, USA

@proceedings{DBLP:conf/async/2001,
  title     = {7th International Symposium on Advanced Research in Asynchronous
               Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake
               City, UT, USA},
  booktitle = {ASYNC},
  publisher = {IEEE Computer Society},
  year      = {2001},
  isbn      = {0-7695-1034-5},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Mark Greenstreet

• Bill Athas:
  Asynchronous Design and the Pursuit of Low Power. 2-
  Electronic Edition (link) BibTeX

Systems/Arithmetic

• Mike J. G. Lewis, L. E. M. Brackenbury:
  Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank. 4-14
  Electronic Edition (link) BibTeX
• P. A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber:
  A Low-Power Self-Timed Viterbi Decoder. 15-24
  Electronic Edition (link) BibTeX
• Gianluca Cornetta, Jordi Cortadella:
  A Multi-Radix Approach to Asynchronous Division. 25-
  Electronic Edition (link) BibTeX

Experiments

• David W. Lloyd, Jim D. Garside:
  A Practical Comparison of Asynchronous Design Styles. 36-45
  Electronic Edition (link) BibTeX
• Ivan E. Sutherland, Scott Fairbanks:
  GasP: A Minimal FIFO Control. 46-53
  Electronic Edition (link) BibTeX
• Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, Kouichi Nagami, Kiyoshi Oguri:
  PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI. 54-
  Electronic Edition (link) BibTeX

Synthesis and Verification

• Chris J. Myers, Hans M. Jacobson:
  Efficient Exact Two-Level Hazard-Free Logic Minimization. 64-73
  Electronic Edition (link) BibTeX
• Robert Berks, Radu Negulescu:
  Partial-Order Correctness-Preserving Properties of Delay-Insensitive Circuits. 74-
  Electronic Edition (link) BibTeX

Handshaking

• Ad M. G. Peeters, Kees van Berkel:
  Synchronous Handshake Circuits. 86-95
  Electronic Edition (link) BibTeX
• Rajit Manohar:
  An Analysis of Reshuffled Handshaking Expansions. 96-
  Electronic Edition (link) BibTeX

Communication

• Joep L. W. Kessels, Ad M. G. Peeters, Torsten Kramer, Markus Feuser, Klaus Ully:
  Designing an Asynchronous Bus Interface. 108-117
  Electronic Edition (link) BibTeX
• W. J. Bainbridge, Stephen B. Furber:
  Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. 118-126
  Electronic Edition (link) BibTeX
• Alexandre Yakovlev, Fei Xia, Delong Shang:
  Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism. 127-
  Electronic Edition (link) BibTeX

Invited Session 2

• Kevin Normoyle:
  Where are the Async Millionaires? 138-
  Electronic Edition (link) BibTeX

Architecture

• Tony Werner, Venkatesh Akella:
  An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. 140-151
  Electronic Edition (link) BibTeX
• Daranee Hormdee, Jim D. Garside:
  AMULET3i Cache Architecture. 152-161
  Electronic Edition (link) BibTeX
• Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno:
  Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. 162-172
  Electronic Edition (link) BibTeX
• William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, Ivan E. Sutherland:
  FLEETzero: An Asynchronous Switching Experiment. 173-
  Electronic Edition (link) BibTeX

Performance Analysis and Optimization

• Ivan E. Sutherland, Jon K. Lexau:
  Designing Fast Asynchronous Circuits. 184-193
  Electronic Edition (link) BibTeX
• Jo C. Ebergen:
  Squaring the FIFO in GasP. 194-205
  Electronic Edition (link) BibTeX
• Mark R. Greenstreet, Brian de Alwis:
  How to Achieve Worst-Case Performance. 206-
  Electronic Edition (link) BibTeX

Invited Session

• Ajay Koche:
  Testing Asynchronous Circuits: Help is on the Way! 218-
  Electronic Edition (link) BibTeX