| 2007 |
|---|
| 7 | EE | Manuel Saldaña,
Lesley Shannon,
Jia Shuo Yue,
Sikang Bian,
John Craig,
Paul Chow:
Routability of Network Topologies in FPGAs.
IEEE Trans. VLSI Syst. 15(8): 948-951 (2007) |
| 2006 |
|---|
| 6 | EE | Arun Patel,
Christopher A. Madill,
Manuel Saldaña,
Chris Comis,
Regis Pomes,
Paul Chow:
A Scalable FPGA-based Multiprocessor.
FCCM 2006: 111-120 |
| 5 | EE | Manuel Saldaña,
Lesley Shannon,
Paul Chow:
The routability of multiprocessor network topologies in FPGAs.
FPGA 2006: 232 |
| 4 | EE | Lesley Shannon,
Blair Fort,
Samir Parikh,
Arun Patel,
Manuel Saldaña,
Paul Chow:
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification.
FPL 2006: 1-6 |
| 3 | EE | Manuel Saldaña,
Paul Chow:
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs.
FPL 2006: 1-6 |
| 2 | EE | Manuel Saldaña,
Lesley Shannon,
Paul Chow:
The routability of multiprocessor network topologies in FPGAs.
SLIP 2006: 49-56 |
| 2005 |
|---|
| 1 | | Lesley Shannon,
Blair Fort,
Samir Parikh,
Arun Patel,
Manuel Saldaña,
Paul Chow:
Designing an FPGA SoC Using a Standardized IP Block Interface.
FPT 2005: 341-342 |
