| 2006 |
|---|
| 4 | EE | Blair Fort,
Davor Capalija,
Zvonko G. Vranesic,
Stephen Dean Brown:
A Multithreaded Soft Processor for SoPC Area Reduction.
FCCM 2006: 131-142 |
| 3 | EE | Lesley Shannon,
Blair Fort,
Samir Parikh,
Arun Patel,
Manuel Saldaña,
Paul Chow:
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification.
FPL 2006: 1-6 |
| 2005 |
|---|
| 2 | | Lesley Shannon,
Blair Fort,
Samir Parikh,
Arun Patel,
Manuel Saldaña,
Paul Chow:
Designing an FPGA SoC Using a Standardized IP Block Interface.
FPT 2005: 341-342 |
| 1 | EE | Franjo Plavec,
Blair Fort,
Zvonko G. Vranesic,
Stephen Dean Brown:
Experiences with Soft-Core Processor Design.
IPDPS 2005 |
