| 2008 |
|---|
| 3 | EE | Jie Jin,
Chi-Ying Tsui:
A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes.
ISLPED 2008: 253-258 |
| 2007 |
|---|
| 2 | EE | Jie Jin,
Chi-Ying Tsui:
Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition.
IEEE Trans. VLSI Syst. 15(10): 1172-1176 (2007) |
| 2006 |
|---|
| 1 | EE | Jie Jin,
Chi-Ying Tsui:
A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications.
ISLPED 2006: 406-411 |
