| 1999 |
|---|
| 9 | EE | Jagannathan Narasimhan,
Kazuo Nakajima,
Chong S. Rim:
A Graph Theoretical Approach for the Yield Enhancement of Reconfigurable VLSI/WSI Arrays.
Discrete Applied Mathematics 90(1-3): 195-221 (1999) |
| 8 | EE | Young-Jun Cha,
Chong S. Rim,
Kazuo Nakajima:
SEGRA: a very fast general area router for multichip modules.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 659-665 (1999) |
| 1997 |
|---|
| 7 | EE | Young-Jun Cha,
Chong S. Rim,
Kazuo Nakajima:
A simple and effective greedy multilayer router for MCMs.
ISPD 1997: 67-72 |
| 1995 |
|---|
| 6 | | Yanghoon Kim,
Chong S. Rim,
Byoungki Min:
A Block Matching Algorithm with 16: 1 Subsampling and Its Hardware Design.
ISCAS 1995: 613-616 |
| 1994 |
|---|
| 5 | | Yhonkyong Choi,
Juhyun Lee,
Chong S. Rim:
Automatic Functional Cell Generation in the Sea-of-Gates Layout Style.
ISCAS 1994: 189-192 |
| 4 | EE | J. Narasimham,
Kazuo Nakajima,
Chong S. Rim,
Anton T. Dahbura:
Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 976-986 (1994) |
| 1992 |
|---|
| 3 | | Ruey-Der Lou,
Majid Sarrafzadeh,
Chong S. Rim,
Kazuo Nakajima,
Sumio Masuda:
General Circular Permutation Layout.
Mathematical Systems Theory 25(4): 269-292 (1992) |
| 1989 |
|---|
| 2 | EE | Chong S. Rim,
Toshinobu Kashiwabara,
Kazuo Nakajima:
Exact algorithms for multilayer topological via minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(11): 1165-1173 (1989) |
| 1 | | Hyeong-Ah Choi,
Kazuo Nakajima,
Chong S. Rim:
Graph Bipartization and via Minimization.
SIAM J. Discrete Math. 2(1): 38-47 (1989) |
