The Journal of Signal Processing Systems, Volume 50

Volume 50, Number 1, January 2008

• Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sung-Fang Tsai, Liang-Gee Chen:
  Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder. 1-17
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• Yu Li, Yun He, Shunliang Mei:
  A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC. 19-32
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• Jonah Probell:
  Architecture Considerations for Multi-Format Programmable Video Processors. 33-39
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• Yanmei Qu, Yun He, Shunliang Mei:
  A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC. 41-51
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• Sung Dae Kim, Myung Hoon Sunwoo:
  ASIP Approach for Implementation of H.264/AVC. 53-67
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• Tsu-Ming Liu, Chen-Yi Lee:
  Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead. 69-80
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• Lingfeng Li, Yang Song, Shen Li, Takeshi Ikenaga, Satoshi Goto:
  A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC. 81-95
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Volume 50, Number 2, February 2008

• Shuvra S. Bhattacharyya, Jarmo Takala, Georgi Gaydadjiev:
  Introduction to the Special Issue on Embedded Computing Systems for DSP. 97-98
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• Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas:
  Calibration of Abstract Performance Models for System-Level Design Space Exploration. 99-114
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• Ye Wen, Selim Gurun, Navraj Chohan, Richard Wolski, Chandra Krintz:
  Accurate and Scalable Simulation of Network of Heterogeneous Sensor Devices. 115-136
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• Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal:
  Scenario Selection and Prediction for DVS-Aware Scheduling of Multimedia Applications. 137-161
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• Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya:
  Memory-constrained Block Processing for DSP Software Optimization. 163-177
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• Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis:
  Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path. 179-200
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• Mladen Berekovic, Mladen Berekovic, Tim Niggemeier:
  A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance. 201-229
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• Eero Aho, Jarno Vanne, Timo D. Hämäläinen:
  Configurable Data Memory for Multimedia Processing. 231-249
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• Stefan Tillich, Martin Feldhofer, Thomas Popp, Johann Großschädl:
  Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box. 251-261
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Volume 50, Number 3, March 2008

• Li Teng, Laiwan Chan:
  Discovering Biclusters by Iteratively Sorting with Weighted Correlation Coefficient in Gene Expression Data. 267-280
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• Benson S. Y. Lam, Alan Wee-Chung Liew, David Keith Smith, Hong Yan:
  A Regularized Clustering Algorithm Based on Calculus of Variations. 281-292
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• Zhaohui Gan, Tommy W. S. Chow, D. Huang:
  Effective Gene Selection Method Using Bayesian Discriminant Based Criterion and Genetic Algorithms. 293-304
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• Yu-Ping Wang, Maheswar Gunampally, Jie Chen, Douglas Bittel, Merlin G. Butler, Wei-Wen Cai:
  A Comparison of Fuzzy Clustering Approaches for Quantification of Microarray Gene Expression. 305-320
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• Robin Kramer, Dong Xu:
  Projecting Gene Expression Trajectories through Inducing Differential Equations from Microarray Time Series Experiments. 321-329
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• Sujimarn Suwannaroj, Mahesan Niranjan:
  Enhancing Automatic Construction of Gene Subnetworks by Integrating Multiple Sources of Information. 331-340
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