M. Aline

2003
3	EE	E. Kinvi-Boh, M. Aline, Olivier Sentieys, Edgar "Dan" Olson: MVL circuit design and characterization at the transistor level using SUS-LOC. ISMVL 2003: 105-110
2001
2	EE	Nadine Azémard, M. Aline, Daniel Auvergne: Delay bound determination for timing closure satisfaction. ISCAS (5) 2001: 375-378
1		Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne: Feasible Delay Bound Definition. VLSI-SOC 2001: 325-335

Coauthor Index

1	Daniel Auvergne	[1] [2]
2	Nadine Azémard (Nadine Azémard-Crestani)	[1] [2]
3	E. Kinvi-Boh	[3]
4	Philippe Maurine	[1]
5	Edgar "Dan" Olson	[3]
6	Olivier Sentieys	[3]

Colors in the list of coauthors