| |
| 2006 | ||
|---|---|---|
| 1 | EE | Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto: Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Transactions 89-A(12): 3560-3568 (2006) |
| 1 | Masanori Hashimoto | [1] |
| 2 | Toshiki Kanamoto | [1] |
| 3 | Hidetoshi Onodera | [1] |
| 4 | Akira Tsuchiya | [1] |