| 2007 |
|---|
| 6 | EE | Koutaro Hachiya,
Takayuki Ohshima,
Hidenari Nakashima,
Masaaki Soda,
Satoshi Goto:
Fast Methods to Estimate Clock Jitter due to Power Supply Noise.
IEICE Transactions 90-A(4): 741-747 (2007) |
| 2006 |
|---|
| 5 | EE | Toshiki Kanamoto,
Shigekiyo Akutsu,
Tamiyo Nakabayashi,
Takahiro Ichinomiya,
Koutaro Hachiya,
Atsushi Kurokawa,
Hiroshi Ishikawa,
Sakae Muromoto,
Hiroyuki Kobayashi,
Masanori Hashimoto:
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation.
IEICE Transactions 89-A(12): 3666-3670 (2006) |
| 4 | EE | Koutaro Hachiya,
Hiroyuki Kobayashi,
Takaaki Okumura,
Takashi Sato,
Hiroki Oka:
A Method to Derive SSO Design Rule Considering Jitter Constraint.
IEICE Transactions 89-A(4): 865-872 (2006) |
| 2005 |
|---|
| 3 | EE | Takashi Sato,
Junji Ichimiya,
Nobuto Ono,
Koutaro Hachiya,
Masanori Hashimoto:
On-chip thermal gradient analysis and temperature flattening for SoC design.
ASP-DAC 2005: 1074-1077 |
| 2 | EE | Achim Basermann,
Uwe Jaekel,
M. Nordhausen,
Koutaro Hachiya:
Parallel iterative solvers for sparse linear systems in circuit simulation.
Future Generation Comp. Syst. 21(8): 1275-1284 (2005) |
| 1 | EE | Takashi Sato,
Junji Ichimiya,
Nobuto Ono,
Koutaro Hachiya,
Masanori Hashimoto:
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design.
IEICE Transactions 88-A(12): 3382-3389 (2005) |
