2007 |
15 | EE | Zhangcai Huang,
Hong Yu,
Atsushi Kurokawa,
Yasuaki Inoue:
Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies.
ASP-DAC 2007: 565-570 |
14 | EE | Hong Yu,
Yasuaki Inoue,
Kazutoshi Sako,
Xiaochuan Hu,
Zhangcai Huang:
An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm.
IEICE Transactions 90-A(10): 2124-2131 (2007) |
13 | EE | Zhangcai Huang,
Yasuaki Inoue,
Hong Yu,
Jun Pan,
Yun Yang,
Quan Zhang,
Shuai Fang:
Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System.
IEICE Transactions 90-A(4): 732-740 (2007) |
12 | EE | Jun Pan,
Yasuaki Inoue,
Zheng Liang,
Zhangcai Huang,
Weilun Huang:
A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect.
IEICE Transactions 90-A(4): 748-755 (2007) |
2006 |
11 | EE | Zhangcai Huang,
Yasuaki Inoue,
Hong Yu,
Quan Zhang:
A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback.
APCCAS 2006: 708-711 |
10 | EE | Hong Yu,
Yasuaki Inoue,
Yuki Matsuya,
Zhangcai Huang:
An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits.
ISCAS 2006 |
9 | EE | Zhangcai Huang,
Yasuaki Inoue,
Quan Zhang,
Yuehu Zhou,
Long Xie,
Harutoshi Ogai:
Behavioral macromodeling of analog LSI implementation for automobile intake system.
ISCAS 2006 |
8 | EE | Hong Yu,
Yasuaki Inoue,
Yuki Matsuya,
Zhangcai Huang:
An Effective Pseudo-Transient Algorithm for Finding Dc Solutions of Nonlinear Circuits.
IEICE Transactions 89-A(10): 2724-2731 (2006) |
7 | EE | Zhangcai Huang,
Atsushi Kurokawa,
Yun Yang,
Hong Yu,
Yasuaki Inoue:
Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay.
IEICE Transactions 89-A(4): 840-846 (2006) |
6 | EE | Atsushi Kurokawa,
Akira Kasebe,
Toshiki Kanamoto,
Yun Yang,
Zhangcai Huang,
Yasuaki Inoue,
Hiroo Masuda:
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.
IEICE Transactions 89-A(4): 847-855 (2006) |
5 | EE | Atsushi Kurokawa,
Hiroo Masuda,
Junko Fujii,
Toshinori Inoshita,
Akira Kasebe,
Zhangcai Huang,
Yasuaki Inoue:
Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays.
IEICE Transactions 89-A(4): 856-864 (2006) |
2005 |
4 | EE | Zhangcai Huang,
Atsushi Kurokawa,
Yasuaki Inoue:
Effective capacitance for gate delay with RC loads.
ISCAS (3) 2005: 2795-2798 |
3 | EE | Zhangcai Huang,
Atsushi Kurokawa,
Yasuaki Inoue,
Junfa Mao:
A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads.
IEICE Transactions 88-A(10): 2562-2569 (2005) |
2 | EE | Zhangcai Huang,
Atsushi Kurokawa,
Jun Pan,
Yasuaki Inoue:
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew.
IEICE Transactions 88-A(12): 3367-3374 (2005) |
1 | EE | Atsushi Kurokawa,
Masanori Hashimoto,
Akira Kasebe,
Zhangcai Huang,
Yun Yang,
Yasuaki Inoue,
Ryosuke Inagaki,
Hiroo Masuda:
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.
IEICE Transactions 88-A(12): 3453-3462 (2005) |